[U-Boot] i.MX51: FEC: Cache coherency problem?

[Aneesh V]

Hi Albert, David,

On Tuesday 19 July 2011 02:41 PM, Albert ARIBAUD wrote:
> Hi David,
>
> Le 19/07/2011 10:58, David Jander a écrit :
>
>>>> 587 flush_cache(&fec->tbd_base[fec->tbd_index], 4);
>>>
>>> This is what is needed assuming the below is initiating a memory to
>>> peripheral DMA. Is your buffer only 4 bytes long?
>>
>> No it isn't. I know, I should flush the whole buffer area, but this
>> was just
>> enough to get the status field flushed, so the FEC started
>> transmitting, and
>> the while loop ended eventually. The result was still not correct, but at
>> least it won't hang.
>
> Seems like you're flushing while the DMA engine is running... That's
> calling for race conditions IMO. You should only have the DMA engine
> running while you are sending something or while you are expecting to
> receive something (U-Boot differs from an OS in that devices are not
> kept running unless actually needed).
>
>> What would be more expensive, flushing just the buffer area, or
>> flush_dcache_all()?
>
> You should call the API for flushing the area only. Obviously, you'll
> flush either just as much, or possibly more (thus take longer) if you
> flush the whole data cache.

Flushing an entire cache line by line is typically not as efficient as
using the special instructions to flush the entire cache(particularly
for large L2 caches). In our experiments on the 1MB L2$ cache on
Cortex-A9 the latter was more than 2x fast compared to the former.

best regards,
Aneesh