[U-Boot] [PATCH] cleanup: Fix typos and misspellings in various files.
Mike Williams
mike at mikebwilliams.com
Fri Jul 22 16:01:30 CEST 2011
Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/address
Signed-off-by: Mike Williams <mike at mikebwilliams.com>
---
arch/arm/cpu/arm720t/lpc2292/mmc_hw.c | 4 ++--
arch/arm/cpu/arm720t/start.S | 2 +-
arch/arm/cpu/arm920t/at91/timer.c | 2 +-
arch/arm/cpu/arm920t/start.S | 4 ++--
arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c | 2 +-
arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h | 2 +-
arch/arm/cpu/ixp/npe/include/IxNpeA.h | 2 +-
arch/arm/cpu/ixp/npe/include/IxQMgr.h | 2 +-
arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h | 2 +-
arch/arm/cpu/lh7a40x/start.S | 2 +-
arch/arm/cpu/sa1100/start.S | 2 +-
arch/m68k/include/asm/fec.h | 2 +-
arch/powerpc/include/asm/cpm_8260.h | 2 +-
arch/powerpc/include/asm/cpm_85xx.h | 2 +-
arch/powerpc/include/asm/ppc440ep_gr.h | 4 ++--
arch/powerpc/include/asm/ppc440epx_grx.h | 4 ++--
arch/powerpc/include/asm/ppc440gx.h | 4 ++--
arch/powerpc/include/asm/ppc440sp.h | 4 ++--
arch/powerpc/include/asm/ppc440spe.h | 4 ++--
arch/sparc/cpu/leon3/usb_uhci.c | 2 +-
arch/x86/cpu/start.S | 2 +-
arch/x86/include/asm/interrupt.h | 2 +-
board/Marvell/common/bootseq.txt | 2 +-
board/Marvell/common/i2c.c | 2 +-
board/Marvell/common/ns16550.h | 2 +-
board/Marvell/include/mv_gen_reg.h | 2 +-
board/bmw/ns16550.h | 2 +-
board/digsy_mtc/eeprom.h | 2 +-
board/evb64260/bootseq.txt | 2 +-
board/evb64260/i2c.c | 2 +-
board/freescale/mpc8266ads/mpc8266ads.c | 2 +-
board/mpl/common/usb_uhci.c | 2 +-
common/cmd_flash.c | 2 +-
common/xyzModem.c | 2 +-
doc/README.m68k | 4 ++--
doc/README.qemu_mips | 2 +-
drivers/net/4xx_enet.c | 2 +-
drivers/net/greth.c | 2 +-
drivers/net/natsemi.c | 2 +-
drivers/net/ns8382x.c | 2 +-
drivers/pci/fsl_pci_init.c | 2 +-
drivers/rtc/mpc5xxx.c | 2 +-
include/commproc.h | 2 +-
include/configs/NETTA.h | 2 +-
include/configs/TQM834x.h | 2 +-
include/galileo/gt64260R.h | 2 +-
include/mpc5xxx_sdma.h | 4 ++--
include/mpc824x.h | 2 +-
48 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
index b4dc4a6..bd6a5b1 100644
--- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
+++ b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
@@ -148,7 +148,7 @@ unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
/* Command 16 to read aBlocks from the MMC/SD - caed */
unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
- /* The addres on the MMC/SD-card is in bytes,
+ /* The address on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
@@ -173,7 +173,7 @@ unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
/* Command 24 to write a block to the MMC/SD - card */
unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
- /* The addres on the MMC/SD-card is in bytes,
+ /* The address on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index e774c3f..46748a1 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -274,7 +274,7 @@ _dynsym_start_ofs:
#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-/* Interupt-Controller base addresses */
+/* Interrupt-Controller base addresses */
INTMR1: .word 0x80000280 @ 32 bit size
INTMR2: .word 0x80001280 @ 16 bit size
INTMR3: .word 0x80002280 @ 8 bit size
diff --git a/arch/arm/cpu/arm920t/at91/timer.c b/arch/arm/cpu/arm920t/at91/timer.c
index f0ad7d6..54b2df0 100644
--- a/arch/arm/cpu/arm920t/at91/timer.c
+++ b/arch/arm/cpu/arm920t/at91/timer.c
@@ -59,7 +59,7 @@ int timer_init(void)
when the value in TC_RC is reached */
writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
- writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
+ writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index a7476b0..e6f6741 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -142,11 +142,11 @@ copyex:
# if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#else
# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
# endif
diff --git a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
index 09f69ce..642e67a 100644
--- a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
+++ b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
@@ -386,7 +386,7 @@ ixQMgrNotificationEnable (IxQMgrQId qId,
&dispatchQInfo[qId].statusMask);
- /* Set the interupt source is this queue is in the range 0-31 */
+ /* Set the interrupt source is this queue is in the range 0-31 */
if (qId < IX_QMGR_MIN_QUEUPP_QID)
{
ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
index 0ee4123..4e0de82 100644
--- a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
+++ b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
@@ -279,7 +279,7 @@ typedef struct
BOOL portInitialized;
UINT32 npeId; /**< NpeId for this port */
IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
- IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */
+ IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
} IxEthAccPortDataInfo;
extern IxEthAccPortDataInfo ixEthAccPortData[];
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeA.h b/arch/arm/cpu/ixp/npe/include/IxNpeA.h
index 7427cc4..90669c2 100644
--- a/arch/arm/cpu/ixp/npe/include/IxNpeA.h
+++ b/arch/arm/cpu/ixp/npe/include/IxNpeA.h
@@ -717,7 +717,7 @@ typedef struct
*/
typedef struct
{
- UINT32 rxBitField; /**< Recieved bit field */
+ UINT32 rxBitField; /**< Received bit field */
UINT32 atmCellHeader; /**< ATM Cell Header */
UINT32 rsvdWord0; /**< Reserved field */
UINT16 currMbufLen; /**< Mbuf Length */
diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgr.h b/arch/arm/cpu/ixp/npe/include/IxQMgr.h
index 165ed96..03d7e07 100644
--- a/arch/arm/cpu/ixp/npe/include/IxQMgr.h
+++ b/arch/arm/cpu/ixp/npe/include/IxQMgr.h
@@ -570,7 +570,7 @@ typedef enum
* @brief Queue interrupt source select.
*
* This enum defines the different source conditions on a queue that result in
- * an interupt being fired by the AQM. Interrupt source is configurable for
+ * an interrupt being fired by the AQM. Interrupt source is configurable for
* queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
* NE(Nearly Empty) status flag.
*
diff --git a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
index f7194e7..b65d621 100644
--- a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
+++ b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
@@ -404,7 +404,7 @@
*
* @def IX_ETH_ACC_RX_FRAME_ETH_Q
*
-* @brief Eth0/Eth1 NPE Frame Recieve Q.
+* @brief Eth0/Eth1 NPE Frame Receive Q.
*
* @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
*
diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S
index 81242b1..a645d65 100644
--- a/arch/arm/cpu/lh7a40x/start.S
+++ b/arch/arm/cpu/lh7a40x/start.S
@@ -124,7 +124,7 @@ reset:
msr cpsr,r0
#define pWDTCTL 0x80001400 /* Watchdog Timer control register */
-#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
+#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */
#define pCLKSET 0x80000420 /* clock divisor register */
/* disable watchdog, set watchdog control register to
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index b27e970..fc2afa4 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -263,7 +263,7 @@ _dynsym_start_ofs:
*/
-/* Interupt-Controller base address */
+/* Interrupt-Controller base address */
IC_BASE: .word 0x90050000
#define ICMR 0x04
diff --git a/arch/m68k/include/asm/fec.h b/arch/m68k/include/asm/fec.h
index cecec59..e8cea45 100644
--- a/arch/m68k/include/asm/fec.h
+++ b/arch/m68k/include/asm/fec.h
@@ -39,7 +39,7 @@ typedef struct cpm_buf_desc {
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h
index 8302404..6a4a51a 100644
--- a/arch/powerpc/include/asm/cpm_8260.h
+++ b/arch/powerpc/include/asm/cpm_8260.h
@@ -117,7 +117,7 @@ typedef struct cpm_buf_desc {
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
index a74a3a1..1681ecd 100644
--- a/arch/powerpc/include/asm/cpm_85xx.h
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -110,7 +110,7 @@ typedef struct cpm_buf_desc {
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
diff --git a/arch/powerpc/include/asm/ppc440ep_gr.h b/arch/powerpc/include/asm/ppc440ep_gr.h
index dfd1532..e790963 100644
--- a/arch/powerpc/include/asm/ppc440ep_gr.h
+++ b/arch/powerpc/include/asm/ppc440ep_gr.h
@@ -182,7 +182,7 @@
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
@@ -192,7 +192,7 @@
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h
index 6c21472..c841f0f 100644
--- a/arch/powerpc/include/asm/ppc440epx_grx.h
+++ b/arch/powerpc/include/asm/ppc440epx_grx.h
@@ -398,7 +398,7 @@
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
@@ -408,7 +408,7 @@
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440gx.h b/arch/powerpc/include/asm/ppc440gx.h
index 6f8581b..9924525 100644
--- a/arch/powerpc/include/asm/ppc440gx.h
+++ b/arch/powerpc/include/asm/ppc440gx.h
@@ -71,7 +71,7 @@
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
@@ -81,7 +81,7 @@
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440sp.h b/arch/powerpc/include/asm/ppc440sp.h
index 4387495..cc2ff68 100644
--- a/arch/powerpc/include/asm/ppc440sp.h
+++ b/arch/powerpc/include/asm/ppc440sp.h
@@ -67,7 +67,7 @@
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
@@ -77,7 +77,7 @@
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440spe.h b/arch/powerpc/include/asm/ppc440spe.h
index bad9a40..d59d7d2 100644
--- a/arch/powerpc/include/asm/ppc440spe.h
+++ b/arch/powerpc/include/asm/ppc440spe.h
@@ -83,7 +83,7 @@
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
@@ -93,7 +93,7 @@
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c
index 8f99e1d..b1269d2 100644
--- a/arch/sparc/cpu/leon3/usb_uhci.c
+++ b/arch/sparc/cpu/leon3/usb_uhci.c
@@ -70,7 +70,7 @@
*
* Interrupt Transfers.
* --------------------
- * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
* will be inserted after the appropriate (depending the interval setting) skeleton TD.
* If an interrupt has been detected the dev->irqhandler is called. The status and number
* of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 7ccc076..6c84c43 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -66,7 +66,7 @@ _start:
movw %ax, %es
movw %ax, %ss
- /* Clear the interupt vectors */
+ /* Clear the interrupt vectors */
lidt blank_idt_ptr
/* Early platform init (setup gpio, etc ) */
diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h
index be52fe4..f33f8ed 100644
--- a/arch/x86/include/asm/interrupt.h
+++ b/arch/x86/include/asm/interrupt.h
@@ -32,7 +32,7 @@
/* arch/x86/cpu/interrupts.c */
void set_vector(u8 intnum, void *routine);
-/* arch/x86/lib/interupts.c */
+/* arch/x86/lib/interrupts.c */
void disable_irq(int irq);
void enable_irq(int irq);
diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt
index e4fefb3..6cae9ea 100644
--- a/board/Marvell/common/bootseq.txt
+++ b/board/Marvell/common/bootseq.txt
@@ -62,7 +62,7 @@ in_flash:
remap gt regs?
map PCI mem/io
map device space
- clear out interupts
+ clear out interrupts
init_timebase
env_init
serial_init
diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c
index 8d87b2d..d53495c 100644
--- a/board/Marvell/common/i2c.c
+++ b/board/Marvell/common/i2c.c
@@ -420,7 +420,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
status = i2c_get_data (data, len);
if (status) {
#ifdef DEBUG_I2C
- printf ("Data not recieved: 0x%02x\n", status);
+ printf ("Data not received: 0x%02x\n", status);
#endif
return status;
}
diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h
index 0a2951b..9306381 100644
--- a/board/Marvell/common/ns16550.h
+++ b/board/Marvell/common/ns16550.h
@@ -51,7 +51,7 @@ struct NS16550
#define dlm ier
#define FCR_FIFO_EN 0x01 /*fifo enable*/
-#define FCR_RXSR 0x02 /*reciever soft reset*/
+#define FCR_RXSR 0x02 /*receiver soft reset*/
#define FCR_TXSR 0x04 /*transmitter soft reset*/
diff --git a/board/Marvell/include/mv_gen_reg.h b/board/Marvell/include/mv_gen_reg.h
index 5e4f076..03fcd88 100644
--- a/board/Marvell/include/mv_gen_reg.h
+++ b/board/Marvell/include/mv_gen_reg.h
@@ -2237,7 +2237,7 @@
#define CHANNEL2_REGISTER10 0x9070
#define CHANNEL2_REGISTER11 0x9074
-/* MPSCs Interupts */
+/* MPSCs Interrupts */
#define MPSC0_CAUSE 0xb824
#define MPSC0_MASK 0xb8a4
diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h
index 8aa251d..2087a4a 100644
--- a/board/bmw/ns16550.h
+++ b/board/bmw/ns16550.h
@@ -37,7 +37,7 @@ struct NS16550 {
#define afr iirfcrafr
#define FCR_FIFO_EN 0x01 /*fifo enable */
-#define FCR_RXSR 0x02 /*reciever soft reset */
+#define FCR_RXSR 0x02 /*receiver soft reset */
#define FCR_TXSR 0x04 /*transmitter soft reset */
#define FCR_DMS 0x08 /* DMA Mode Select */
diff --git a/board/digsy_mtc/eeprom.h b/board/digsy_mtc/eeprom.h
index 39e0378..fd11555 100644
--- a/board/digsy_mtc/eeprom.h
+++ b/board/digsy_mtc/eeprom.h
@@ -27,6 +27,6 @@
#define EEPROM_ADDR_IDENT 0 /* identification word offset */
#define EEPROM_ADDR_LEN_SYS 2 /* system area lenght offset */
#define EEPROM_ADDR_LEN_SYSCFG 4 /* system config area length offset */
-#define EEPROM_ADDR_ETHADDR 23 /* ethernet addres offset */
+#define EEPROM_ADDR_ETHADDR 23 /* ethernet address offset */
#endif
diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt
index e4fefb3..6cae9ea 100644
--- a/board/evb64260/bootseq.txt
+++ b/board/evb64260/bootseq.txt
@@ -62,7 +62,7 @@ in_flash:
remap gt regs?
map PCI mem/io
map device space
- clear out interupts
+ clear out interrupts
init_timebase
env_init
serial_init
diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c
index c62b647..88d0dac 100644
--- a/board/evb64260/i2c.c
+++ b/board/evb64260/i2c.c
@@ -306,7 +306,7 @@ i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data,
status = i2c_get_data(data, len);
if (status) {
#ifdef DEBUG_I2C
- printf("Data not recieved: 0x%02x\n", status);
+ printf("Data not received: 0x%02x\n", status);
#endif
return status;
}
diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c
index 66acc41..2caf4aa 100644
--- a/board/freescale/mpc8266ads/mpc8266ads.c
+++ b/board/freescale/mpc8266ads/mpc8266ads.c
@@ -392,7 +392,7 @@ phys_size_t initdram(int board_type)
The 11th column addre will still be mucxed correctly onto the bus.
Also be aware that the MPC8266ADS board Rev B has not connected
- Row addres 13 to anything.
+ Row address 13 to anything.
The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
*/
diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c
index a009437..89d2e0a 100644
--- a/board/mpl/common/usb_uhci.c
+++ b/board/mpl/common/usb_uhci.c
@@ -67,7 +67,7 @@
*
* Interrupt Transfers.
* --------------------
- * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
* will be inserted after the appropriate (depending the interval setting) skeleton TD.
* If an interrupt has been detected the dev->irqhandler is called. The status and number
* of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
diff --git a/common/cmd_flash.c b/common/cmd_flash.c
index bd49b79..5508d73 100644
--- a/common/cmd_flash.c
+++ b/common/cmd_flash.c
@@ -139,7 +139,7 @@ int flash_sect_roundb (ulong *addr)
} /* bank */
}
if (!found) {
- /* error, addres not in flash */
+ /* error, address not in flash */
printf("Error: end address (0x%08lx) not in flash!\n", *addr);
return 1;
}
diff --git a/common/xyzModem.c b/common/xyzModem.c
index 7a46805..a1f955b 100644
--- a/common/xyzModem.c
+++ b/common/xyzModem.c
@@ -786,7 +786,7 @@ xyzModem_stream_terminate (bool abort, int (*getc) (void))
ZM_DEBUG (zm_dprintf ("Engaging cleanup mode...\n"));
/*
* Consume any trailing crap left in the inbuffer from
- * previous recieved blocks. Since very few files are an exact multiple
+ * previous received blocks. Since very few files are an exact multiple
* of the transfer block size, there will almost always be some gunk here.
* If we don't eat it now, RedBoot will think the user typed it.
*/
diff --git a/doc/README.m68k b/doc/README.m68k
index 3766b33..c85febc 100644
--- a/doc/README.m68k
+++ b/doc/README.m68k
@@ -111,7 +111,7 @@ CONFIG_SYS_MBAR -- defines the base address of the MCF5272 configuration registe
CONFIG_SYS_INIT_RAM_ADDR
-- defines the base address of the MCF5272 internal SRAM
CONFIG_SYS_ENET_BD_BASE
- -- defines the base addres of the FEC buffer descriptors
+ -- defines the base address of the FEC buffer descriptors
CONFIG_SYS_SCR -- defines the contents of the System Configuration Register
CONFIG_SYS_SPR -- defines the contents of the System Protection Register
@@ -138,7 +138,7 @@ CONFIG_SYS_INIT_RAM_ADDR
CONFIG_SYS_INT_FLASH_BASE
-- defines the base address of the MCF5282 internal Flash memory
CONFIG_SYS_ENET_BD_BASE
- -- defines the base addres of the FEC buffer descriptors
+ -- defines the base address of the FEC buffer descriptors
CONFIG_SYS_MFD
-- defines the PLL Multiplication Factor Devider
diff --git a/doc/README.qemu_mips b/doc/README.qemu_mips
index 3985264..e6a3855 100644
--- a/doc/README.qemu_mips
+++ b/doc/README.qemu_mips
@@ -24,7 +24,7 @@ you can downland
#config to build the kernel
qemu_mips_defconfig
-#patch to fix mips interupt init on 2.6.24.y kernel
+#patch to fix mips interrupt init on 2.6.24.y kernel
qemu_mips_kernel.patch
initrd.gz
vmlinux
diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
index b1763b1..e616aaf 100644
--- a/drivers/net/4xx_enet.c
+++ b/drivers/net/4xx_enet.c
@@ -1704,7 +1704,7 @@ int enetInt (struct eth_device *dev)
rc = 0;
}
- /* handle MAL RX EOB interupt from a receive */
+ /* handle MAL RX EOB interrupt from a receive */
/* check for EOB on valid channels */
if (uic_mal & UIC_MAL_RXEOB) {
mal_eob = mfdcr(MAL0_RXEOBISR);
diff --git a/drivers/net/greth.c b/drivers/net/greth.c
index 6c32226..2aab52f 100644
--- a/drivers/net/greth.c
+++ b/drivers/net/greth.c
@@ -576,7 +576,7 @@ int greth_recv(struct eth_device *dev)
GRETH_REGORIN(®s->control, GRETH_RXEN);
}
done:
- /* return positive length of packet or 0 if non recieved */
+ /* return positive length of packet or 0 if non received */
return len;
}
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index 14b2d35..9386adf 100644
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -282,7 +282,7 @@ OUTL(struct eth_device *dev, int command, u_long addr)
* ready to send and receive packets.
*
* Side effects:
- * leaves the natsemi initialized, and ready to recieve packets.
+ * leaves the natsemi initialized, and ready to receive packets.
*
* Returns: struct eth_device *: pointer to NIC data structure
*/
diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c
index 45402cc..6dfcd0e 100644
--- a/drivers/net/ns8382x.c
+++ b/drivers/net/ns8382x.c
@@ -299,7 +299,7 @@ OUTL(struct eth_device *dev, int command, u_long addr)
* Description: Retrieves the MAC address of the card, and sets up some
* globals required by other routines, and initializes the NIC, making it
* ready to send and receive packets.
- * Side effects: initializes ns8382xs, ready to recieve packets.
+ * Side effects: initializes ns8382xs, ready to receive packets.
* Returns: int: number of cards found
*/
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index ab461b4..7f601d4 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -316,7 +316,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
hose->current_busno = hose->first_busno;
out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
- out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except
+ out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
* - Master abort (pci)
* - Master PERR (pci)
* - ICCA (PCIe)
diff --git a/drivers/rtc/mpc5xxx.c b/drivers/rtc/mpc5xxx.c
index ec0b0ef..6b3d5e6 100644
--- a/drivers/rtc/mpc5xxx.c
+++ b/drivers/rtc/mpc5xxx.c
@@ -44,7 +44,7 @@ typedef struct rtc5200 {
volatile ulong aier; /* MBAR+0x80C: alarm and interrupt enable register */
volatile ulong ctr; /* MBAR+0x810: current time register */
volatile ulong cdr; /* MBAR+0x814: current data register */
- volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interupt register */
+ volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interrupt register */
volatile ulong piber; /* MBAR+0x81C: periodic interrupt and bus error register */
volatile ulong trdr; /* MBAR+0x820: test register/divides register */
} RTC5200;
diff --git a/include/commproc.h b/include/commproc.h
index a69a809..8b8cc45 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -108,7 +108,7 @@ typedef struct cpm_buf_desc {
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index bdc93b6..92b7d6a 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -589,7 +589,7 @@
+------+----------------+------------------------------------------------------------
| # | Name | Comment
+------+----------------+------------------------------------------------------------
- | IRQ1 | UINTER_3V | S interupt chips interrupt (common)
+ | IRQ1 | UINTER_3V | S interrupt chips interrupt (common)
| IRQ3 | IRQ_DSP | DSP interrupt
| IRQ4 | IRQ_DSP1 | Extra DSP interrupt
+------+----------------+------------------------------------------------------------
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 7c9dd79..5cd517d 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -39,7 +39,7 @@
#define CONFIG_SYS_TEXT_BASE 0x80000000
-/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
+/* IMMR Base Address Register, use Freescale default: 0xff400000 */
#define CONFIG_SYS_IMMR 0xff400000
/* System clock. Primary input clock when in PCI host mode */
diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h
index c2cfb06..b55da9d 100644
--- a/include/galileo/gt64260R.h
+++ b/include/galileo/gt64260R.h
@@ -1182,7 +1182,7 @@
#define CHANNEL2_REGISTER10 0x9070
#define CHANNEL2_REGISTER11 0x9074
-/* MPSCs Interupts */
+/* MPSCs Interrupts */
#define MPSC0_CAUSE 0xb824
#define MPSC0_MASK 0xb8a4
diff --git a/include/mpc5xxx_sdma.h b/include/mpc5xxx_sdma.h
index 8b740e4..821ac0a 100644
--- a/include/mpc5xxx_sdma.h
+++ b/include/mpc5xxx_sdma.h
@@ -82,11 +82,11 @@ ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH).
sdma->IntPend = (1 << tasknum); \
}
-/* get interupt pending bit of a task */
+/* get interrupt pending bit of a task */
#define SDMA_GET_PENDINGBIT(tasknum) \
((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum)))
-/* get interupt mask bit of a task */
+/* get interrupt mask bit of a task */
#define SDMA_GET_MASKBIT(tasknum) \
((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum)))
diff --git a/include/mpc824x.h b/include/mpc824x.h
index fca9371..cb84458 100644
--- a/include/mpc824x.h
+++ b/include/mpc824x.h
@@ -258,7 +258,7 @@
#define PLTR 0x8000000d /* PCI Latancy Timer Register */
#define PHTR 0x8000000e /* PCI Header Type Register */
#define BISTCTRL 0x8000000f /* BIST Control */
-#define LMBAR 0x80000010 /* Local Base Addres Register */
+#define LMBAR 0x80000010 /* Local Base Address Register */
#define PCSRBAR 0x80000014 /* PCSR Base Address Register */
#define ILR 0x8000003c /* PCI Interrupt Line Register */
#define IPR 0x8000003d /* Interrupt Pin Register */
--
1.7.3.4
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