[U-Boot] [PATCH] ARM: add marvell specific cache operation

[Lei Wen]

Hi Prafulla,

On Thu, Jun 16, 2011 at 5:31 PM, Prafulla Wadaskar <prafulla at marvell.com> wrote:
>
>
>> -----Original Message-----
>> From: Lei Wen [mailto:leiwen at marvell.com]
>> Sent: Thursday, June 16, 2011 2:34 PM
>> To: u-boot at lists.denx.de; Prafulla Wadaskar; Wadaskar at marvell.com;
>> Prafulla Wadaskar; adrian.wenl at gmail.com
>> Subject: [PATCH] ARM: add marvell specific cache operation
>>
>> For Marvell sheeva 88SV331xV5 core, it has one special cache asm code
>> to do the clean and valid in one line.
>>
>> Signed-off-by: Lei Wen <leiwen at marvell.com>
>> ---
>>  arch/arm/lib/cache.c |    4 ++++
>>  1 files changed, 4 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
>> index 30686fe..ae8f7e0 100644
>> --- a/arch/arm/lib/cache.c
>> +++ b/arch/arm/lib/cache.c
>> @@ -33,11 +33,15 @@ void  flush_cache (unsigned long dummy1, unsigned
>> long dummy2)
>>       arm1136_cache_flush();
>>  #endif
>>  #ifdef CONFIG_ARM926EJS
>> +#if defined(CONFIG_SHEEVA_88SV331xV5)
>> +     asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
>> +#else
>
> Hi Lei
> I had pushed similar code long back but it was not accepted at that time.
> You may push this with proper explanation-
> 1. What this code exactly does and how this change is important for SHEEVA SoCs and boards mainlined so far.

Thanks for your suggestion.

The original implementation only drain write buffer. It cannot assure
that when using dma from device to memory,
the device cannot read the obsolete content of that range. Only
invalidate cache would do that way.

This new adding assemble code for flushing has this meaning as:
"DCache Clean All and Invalidate. Cleans all lines in the DCache, then
invalidates the cache."
It is slightly different from common arm core, as when we want invalidate the
cache, we need to invalidate each cache entry.

That is the reason why I add this specific implementation for Marvell core only.

Best regards,
Lei