[U-Boot] [PATCH 1/2 V3] AT91: Makes AT91SAM9RL SoC build correctly against u-boot-atmel/master

[Hong Xu]

ping ...

On 06/15/2011 11:11 AM, Hong Xu wrote:
> Rework for AT91SAM9RL SoC, makes it build again.
> Based on the work for AT91SAM9260-EK.
>
> Signed-off-by: Hong Xu <hong.xu at atmel.com>
> ---
> Changes since V2
> - No at91_serial_hw_init, no CONFIG_USARTx anymore.
> - Removed SZ_* macros - though I don't have the reason found in code :)
> - Add definitions for all ATMEL_BASE_CSx
>
> Thanks!
>
> arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c | 45 ++----
> arch/arm/include/asm/arch-at91/at91sam9rl.h | 177 ++++++++++----------
> arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h | 121 +++++---------
> 3 files changed, 141 insertions(+), 202 deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
> b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
> index 4f570f4..c2a6584 100644
> --- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
> +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
> @@ -23,77 +23,58 @@
> */
>
> #include <common.h>
> +#include <asm/io.h>
> #include <asm/arch/at91_common.h>
> #include <asm/arch/at91_pmc.h>
> #include <asm/arch/gpio.h>
> -#include <asm/arch/io.h>
>
> void at91_serial0_hw_init(void)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
> + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
>
> at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */
> at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* RXD0 */
> - writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
> + writel(1 << ATMEL_ID_US0, &pmc->pcer);
> }
>
> void at91_serial1_hw_init(void)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
> + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
>
> at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
> at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */
> - writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
> + writel(1 << ATMEL_ID_US1, &pmc->pcer);
> }
>
> void at91_serial2_hw_init(void)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
> + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
>
> at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
> at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */
> - writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
> + writel(1 << ATMEL_ID_US2, &pmc->pcer);
> }
>
> -void at91_serial3_hw_init(void)
> +void at91_seriald_hw_init(void)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
> + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
>
> at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */
> at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
> - writel(1 << AT91_ID_SYS, &pmc->pcer);
> + writel(1 << ATMEL_ID_SYS, &pmc->pcer);
> }
>
> -void at91_serial_hw_init(void)
> -{
> -#ifdef CONFIG_USART0
> - at91_serial0_hw_init();
> -#endif
> -
> -#ifdef CONFIG_USART1
> - at91_serial1_hw_init();
> -#endif
> -
> -#ifdef CONFIG_USART2
> - at91_serial2_hw_init();
> -#endif
> -
> -#ifdef CONFIG_USART3 /* DBGU */
> - at91_serial3_hw_init();
> -#endif
> -}
> -
> -#ifdef CONFIG_HAS_DATAFLASH
> +#ifdef CONFIG_HAS_DATAFLASH || defined(CONFIG_ATMEL_SPI)
> void at91_spi0_hw_init(unsigned long cs_mask)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
> + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
>
> at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */
> at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */
> at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */
>
> /* Enable clock */
> - writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
> + writel(1 << ATMEL_ID_SPI, &pmc->pcer);
>
> if (cs_mask & (1 << 0)) {
> at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
> diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h
> b/arch/arm/include/asm/arch-at91/at91sam9rl.h
> index 8eb0d4f..dfaafee 100644
> --- a/arch/arm/include/asm/arch-at91/at91sam9rl.h
> +++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h
> @@ -14,117 +14,110 @@
> #ifndef AT91SAM9RL_H
> #define AT91SAM9RL_H
>
> +#define CONFIG_ARM926EJS /* ARM926EJS Core */
> +#define CONFIG_AT91FAMILY /* it's a member of AT91 */
> /*
> * Peripheral identifiers/interrupts.
> */
> -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
> -#define AT91_ID_SYS 1 /* System Controller */
> -#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
> -#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
> -#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
> -#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
> -#define AT91SAM9RL_ID_US0 6 /* USART 0 */
> -#define AT91SAM9RL_ID_US1 7 /* USART 1 */
> -#define AT91SAM9RL_ID_US2 8 /* USART 2 */
> -#define AT91SAM9RL_ID_US3 9 /* USART 3 */
> -#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
> -#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
> -#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
> -#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
> -#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
> -#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
> -#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
> -#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
> -#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
> -#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
> -#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
> -#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
> -#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
> -#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
> -#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
> -#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
> -
> -#define AT91_SDRAMC_BASE 0xffffea00
> -#define AT91_SMC_BASE 0xffffec00
> -#define AT91_MATRIX_BASE 0xffffee00
> -#define AT91_PIO_BASE 0xfffff400
> -#define AT91_PMC_BASE 0xfffffc00
> -#define AT91_RSTC_BASE 0xfffffd00
> -#define AT91_PIT_BASE 0xfffffd30
> -#define AT91_WDT_BASE 0xfffffd40
> -
> -#ifdef CONFIG_AT91_LEGACY
> +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
> +#define ATMEL_ID_SYS 1 /* System Controller */
> +#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
> +#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
> +#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */
> +#define ATMEL_ID_PIOD 5 /* Parallel IO Controller D */
> +#define ATMEL_ID_US0 6 /* USART 0 */
> +#define ATMEL_ID_US1 7 /* USART 1 */
> +#define ATMEL_ID_US2 8 /* USART 2 */
> +#define ATMEL_ID_US3 9 /* USART 3 */
> +#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */
> +#define ATMEL_ID_TWI0 11 /* TWI 0 */
> +#define ATMEL_ID_TWI1 12 /* TWI 1 */
> +#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */
> +#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
> +#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
> +#define ATMEL_ID_TC0 16 /* Timer Counter 0 */
> +#define ATMEL_ID_TC1 17 /* Timer Counter 1 */
> +#define ATMEL_ID_TC2 18 /* Timer Counter 2 */
> +#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */
> +#define ATMEL_ID_TSC 20 /* Touch Screen Controller */
> +#define ATMEL_ID_DMA 21 /* DMA Controller */
> +#define ATMEL_ID_UDPHS 22 /* USB Device HS */
> +#define ATMEL_ID_LCDC 23 /* LCD Controller */
> +#define ATMEL_ID_AC97C 24 /* AC97 Controller */
> +#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
>
> /*
> * User Peripheral physical base addresses.
> */
> -#define AT91SAM9RL_BASE_TCB0 0xfffa0000
> -#define AT91SAM9RL_BASE_TC0 0xfffa0000
> -#define AT91SAM9RL_BASE_TC1 0xfffa0040
> -#define AT91SAM9RL_BASE_TC2 0xfffa0080
> -#define AT91SAM9RL_BASE_MCI 0xfffa4000
> -#define AT91SAM9RL_BASE_TWI0 0xfffa8000
> -#define AT91SAM9RL_BASE_TWI1 0xfffac000
> -#define AT91SAM9RL_BASE_US0 0xfffb0000
> -#define AT91SAM9RL_BASE_US1 0xfffb4000
> -#define AT91SAM9RL_BASE_US2 0xfffb8000
> -#define AT91SAM9RL_BASE_US3 0xfffbc000
> -#define AT91SAM9RL_BASE_SSC0 0xfffc0000
> -#define AT91SAM9RL_BASE_SSC1 0xfffc4000
> -#define AT91SAM9RL_BASE_PWMC 0xfffc8000
> -#define AT91SAM9RL_BASE_SPI 0xfffcc000
> -#define AT91SAM9RL_BASE_TSC 0xfffd0000
> -#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
> -#define AT91SAM9RL_BASE_AC97C 0xfffd8000
> -#define AT91_BASE_SYS 0xffffc000
> +#define ATMEL_BASE_TCB0 0xfffa0000
> +#define ATMEL_BASE_TC0 0xfffa0000
> +#define ATMEL_BASE_TC1 0xfffa0040
> +#define ATMEL_BASE_TC2 0xfffa0080
> +#define ATMEL_BASE_MCI 0xfffa4000
> +#define ATMEL_BASE_TWI0 0xfffa8000
> +#define ATMEL_BASE_TWI1 0xfffac000
> +#define ATMEL_BASE_US0 0xfffb0000
> +#define ATMEL_BASE_US1 0xfffb4000
> +#define ATMEL_BASE_US2 0xfffb8000
> +#define ATMEL_BASE_US3 0xfffbc000
> +#define ATMEL_BASE_SSC0 0xfffc0000
> +#define ATMEL_BASE_SSC1 0xfffc4000
> +#define ATMEL_BASE_PWMC 0xfffc8000
> +#define ATMEL_BASE_SPI 0xfffcc000
> +#define ATMEL_BASE_SPI0 0xfffcc000
> +#define ATMEL_BASE_TSC 0xfffd0000
> +#define ATMEL_BASE_UDPHS 0xfffd4000
> +#define ATMEL_BASE_AC97C 0xfffd8000
> +#define ATMEL_BASE_SYS 0xffffc000
>
> /*
> - * System Peripherals (offset from AT91_BASE_SYS)
> + * System Peripherals
> */
> -#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
> -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
> -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
> -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
> -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
> -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
> -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
> -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
> -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
> -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
> -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
> -#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
> -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
> -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
> -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
> -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
> -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
> -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
> -#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
> -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
> -#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
> -
> -#define AT91_USART0 AT91SAM9RL_BASE_US0
> -#define AT91_USART1 AT91SAM9RL_BASE_US1
> -#define AT91_USART2 AT91SAM9RL_BASE_US2
> -#define AT91_USART3 AT91SAM9RL_BASE_US3
> -
> -#endif /* CONFIG_AT91_LEGACY */
> +#define ATMEL_BASE_DMA 0xffffe600
> +#define ATMEL_BASE_ECC 0xffffe800
> +#define ATMEL_BASE_SDRAMC 0xffffea00
> +#define ATMEL_BASE_SMC 0xffffec00
> +#define ATMEL_BASE_MATRIX 0xffffee00
> +#define ATMEL_BASE_CCFG 0xffffef10
> +#define ATMEL_BASE_AIC 0xfffff000
> +#define ATMEL_BASE_DBGU 0xfffff200
> +#define ATMEL_BASE_PIOA 0xfffff400
> +#define ATMEL_BASE_PIOB 0xfffff600
> +#define ATMEL_BASE_PIOC 0xfffff800
> +#define ATMEL_BASE_PIOD 0xfffffa00
> +#define ATMEL_BASE_PMC 0xfffffc00
> +#define ATMEL_BASE_RSTC 0xfffffd00
> +#define ATMEL_BASE_SHDWC 0xfffffd10
> +#define ATMEL_BASE_RTT 0xfffffd20
> +#define ATMEL_BASE_PIT 0xfffffd30
> +#define ATMEL_BASE_WDT 0xfffffd40
> +#define ATMEL_BASE_SCKCR 0xfffffd50
> +#define ATMEL_BASE_GPBR 0xfffffd60
> +#define ATMEL_BASE_RTC 0xfffffe00
>
> /*
> * Internal Memory.
> */
> -#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
> -#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
> +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
> +#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
>
> -#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
> -#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
> +#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */
> +#define ATMEL_UHP_BASE 0x00600000 /* USB Device HS controller */
>
> -#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
> -#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */
> +/*
> + * External memory
> + */
> +#define ATMEL_BASE_CS0 0x10000000
> +#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
> +#define ATMEL_BASE_CS2 0x30000000
> +#define ATMEL_BASE_CS3 0x40000000 /* NAND */
> +#define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */
> +#define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */
>
> +#define ATMEL_PIO_PORTS 4
> /*
> * Cpu Name
> */
> -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9RL"
> +#define ATMEL_CPU_NAME "AT91SAM9RL"
>
> #endif
> diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
> b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
> index af8d914..295f768 100644
> --- a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
> +++ b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
> @@ -14,83 +14,48 @@
> #ifndef AT91SAM9RL_MATRIX_H
> #define AT91SAM9RL_MATRIX_H
>
> -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration
> Register 0 */
> -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration
> Register 1 */
> -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration
> Register 2 */
> -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration
> Register 3 */
> -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration
> Register 4 */
> -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration
> Register 5 */
> -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
> -#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
> -#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
> -#define AT91_MATRIX_ULBT_FOUR (2 << 0)
> -#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
> -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
> -
> -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration
> Register 0 */
> -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration
> Register 1 */
> -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration
> Register 2 */
> -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration
> Register 3 */
> -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration
> Register 4 */
> -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration
> Register 5 */
> -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed
> Cycles for a Burst */
> -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
> -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
> -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
> -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
> -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default
> Master */
> -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
> -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
> -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
> -
> -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A
> for Slave 0 */
> -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A
> for Slave 1 */
> -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A
> for Slave 2 */
> -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A
> for Slave 3 */
> -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A
> for Slave 4 */
> -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A
> for Slave 5 */
> -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
> -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
> -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
> -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
> -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
> -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
> -
> -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control
> Register */
> -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0
> (ARM926EJ-S Instruction Master) */
> -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1
> (ARM926EJ-S Data Master) */
> -#define AT91_MATRIX_RCB2 (1 << 2)
> -#define AT91_MATRIX_RCB3 (1 << 3)
> -#define AT91_MATRIX_RCB4 (1 << 4)
> -#define AT91_MATRIX_RCB5 (1 << 5)
> -
> -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration
> Register */
> -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory
> block */
> -#define AT91_MATRIX_ITCM_0 (0 << 0)
> -#define AT91_MATRIX_ITCM_16 (5 << 0)
> -#define AT91_MATRIX_ITCM_32 (6 << 0)
> -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory
> block */
> -#define AT91_MATRIX_DTCM_0 (0 << 4)
> -#define AT91_MATRIX_DTCM_16 (5 << 4)
> -#define AT91_MATRIX_DTCM_32 (6 << 4)
> -
> -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select
> Assignment Register */
> -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
> -#define AT91_MATRIX_CS1A_SMC (0 << 1)
> -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
> -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
> -#define AT91_MATRIX_CS3A_SMC (0 << 3)
> -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
> -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
> -#define AT91_MATRIX_CS4A_SMC (0 << 4)
> -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
> -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
> -#define AT91_MATRIX_CS5A_SMC (0 << 5)
> -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
> -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
> -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
> -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
> -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
> -
> +#ifndef __ASSEMBLY__
> +
> +struct at91_matrix {
> + u32 mcfg[16]; /* Master Configuration Registers */
> + u32 scfg[16]; /* Slave Configuration Registers */
> + u32 pras[16][2]; /* Priority Assignment Slave Registers */
> + u32 mrcr; /* Master Remap Control Register */
> + u32 filler[7];
> + u32 ebicsa; /* EBI Chip Select Assignment Register */
> +};
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
> +#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
> +#define AT91_MATRIX_ULBT_FOUR (2 << 0)
> +#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
> +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
> +
> +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
> +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
> +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
> +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
> +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
> +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
> +
> +#define AT91_MATRIX_M0PR_SHIFT 0
> +#define AT91_MATRIX_M1PR_SHIFT 4
> +#define AT91_MATRIX_M2PR_SHIFT 8
> +#define AT91_MATRIX_M3PR_SHIFT 12
> +#define AT91_MATRIX_M4PR_SHIFT 16
> +#define AT91_MATRIX_M5PR_SHIFT 20
> +
> +#define AT91_MATRIX_RCB0 (1 << 0)
> +#define AT91_MATRIX_RCB1 (1 << 1)
> +
> +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
> +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
> +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
> +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
> +#define AT91_MATRIX_DBPUC (1 << 8)
> +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
> +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
>
> #endif
> --
> 1.7.3.3
>