[U-Boot] [u-boot-release] [PATCH 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

[York Sun]

On Wed, 2011-03-02 at 13:46 -0600, Timur Tabi wrote:
> York Sun wrote:
> >> > if (wrrec_mclk & 1)
> >> > 	wrrec_mclk++;
> >> > 
> > Only 9, 11, 13, 15 need to round up.
> 
> What are all the possible values for wrrec_mclk?
> 

There is no limitation on register timing_cfg_1[wrrec_mclk]. It can be
any value. The limitation comes from JEDEC spec on mode register MR0.
The write recovery for autoprecharge is within the values of 5, 6, 7, 8,
10, 12, 14, 16.

York