[U-Boot] [PATCH 4/5] standard SCI support

[Nobuhiro Iwamatsu]

Hi,

2011/3/2 Yoshinori Sato <ysato at users.sourceforge.jp>:
> h8300 have simlar sh serial I/F.
> It without FIFO.
> This changes support of no FIFO.
>
> Signed-off-by: Yoshinori Sato <ysato at users.sourceforge.jp>
> ---
>  drivers/serial/serial_sh.c |   74 +++++++++++++++++++++++++++++++---
>  drivers/serial/serial_sh.h |   93 +++++++++++++++-----------------------------
>  2 files changed, 98 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
> index fcf69ab..b6c800d 100644
> --- a/drivers/serial/serial_sh.c
> +++ b/drivers/serial/serial_sh.c
> @@ -39,18 +39,73 @@
>  # error "Default SCIF doesn't set....."
>  #endif
>
> -#if defined(CONFIG_SCIF_A)
> -       #define SCIF_BASE_PORT  PORT_SCIFA
> +#if defined(CONFIG_SCI)
> +# define PORT_TYPE     PORT_SCI
> +#elif defined(CONFIG_SCIF_A)
> +# define PORT_TYPE     PORT_SCIFA
>  #else
> -       #define SCIF_BASE_PORT  PORT_SCIF
> +# define PORT_TYPE     PORT_SCIF
>  #endif
>
>  static struct uart_port sh_sci = {
>        .membase        = (unsigned char*)SCIF_BASE,
>        .mapbase        = SCIF_BASE,
> -       .type           = SCIF_BASE_PORT,
> +       .type           = PORT_TYPE,
>  };
>
> +/* TDRE / RDRF emulation for RX610 */
> +/* RX610's SCI don't have TDRE and RDRF in SSR
> +   This part emulate these flags of IR */
> +#if defined(CONFIG_CPU_RX610)
> +

<snip>

> +#elif defined(CONFIG_RX)
> +# define SCSPTR0 0x00088240            /* 8 bit SCI */
> +# define SCSPTR1 0x00088248            /* 8 bit SCI */
> +# define SCSPTR2 0x00088250            /* 8 bit SCI */
> +# define SCSPTR3 0x00088258            /* 8 bit SCI */
> +# define SCSPTR4 0x00088260            /* 8 bit SCI */
> +# define SCSPTR5 0x00088268            /* 8 bit SCI */
> +# define SCSPTR6 0x00088270            /* 8 bit SCI */
> +# define SCSCR_INIT(port)      0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
>  #else
>  # error CPU subtype not defined
>  #endif

<snip>


> @@ -437,7 +449,7 @@ static inline void sci_##name##_out(struct uart_port *port,\
>                                sh4_scif_offset, sh4_scif_size) \
>        CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
>  #endif
> -#elif defined(__H8300H__) || defined(__H8300S__)
> +#elif defined(CONFIG_H8300) || defined(CONFIG_RX)
>  #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
>                                sh4_sci_offset, sh4_sci_size, \
>                                sh3_scif_offset, sh3_scif_size,\

<snip>

> @@ -512,6 +524,13 @@ SCIF_FNS(SCFER,  0x10, 16)
>  SCIF_FNS(SCFCR,  0x18, 16)
>  SCIF_FNS(SCFDR,  0x1c, 16)
>  SCIF_FNS(SCLSR,  0x24, 16)
> +#elif defined(CONFIG_CPU_RX610)
> +SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
> +SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
> +SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
> +SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
> +SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
> +SCIF_FNS(SCLSR,                                0,  0, 0x28, 16)
>  #else
>  /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
>  /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
> @@ -552,48 +571,6 @@ SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)

Why do you use CPU_RX610 and CONFIG_RX ?
Is these necessary for support of H8300 support?

Best regards,
  Nobuhiro
-- 
Nobuhiro Iwamatsu
   iwamatsu at {nigauri.org / debian.org}
   GPG ID: 40AD1FA6