[U-Boot] [PATCH] powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
Kumar Gala
galak at kernel.crashing.org
Mon Mar 7 05:16:21 CET 2011
From: Prabhakar Kushwaha <prabhakar at freescale.com>
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
arch/powerpc/cpu/mpc85xx/p1021_serdes.c | 49 ++++++++++++++++++++++++++++-
arch/powerpc/include/asm/config_mpc85xx.h | 8 +++++
drivers/pci/fsl_pci_init.c | 7 ++++
include/pci.h | 1 +
4 files changed, 64 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
index 457ab5d..1849c16 100644
--- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -26,6 +26,24 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
+typedef struct serdes_85xx {
+ u32 srdscr0; /* 0x00 - SRDS Control Register 0 */
+ u32 srdscr1; /* 0x04 - SRDS Control Register 1 */
+ u32 srdscr2; /* 0x08 - SRDS Control Register 2 */
+ u32 srdscr3; /* 0x0C - SRDS Control Register 3 */
+ u32 srdscr4; /* 0x10 - SRDS Control Register 4 */
+} serdes_85xx_t;
+#define FSL_SRDSCR3_EIC0(x) (((x) & 0x1f) << 8)
+#define FSL_SRDSCR3_EIC0_MASK FSL_SRDSCR3_EIC0(0x1f)
+#define FSL_SRDSCR3_EIC1(x) (((x) & 0x1f) << 0)
+#define FSL_SRDSCR3_EIC1_MASK FSL_SRDSCR3_EIC1(0x1f)
+#define FSL_SRDSCR4_EIC2(x) (((x) & 0x1f) << 8)
+#define FSL_SRDSCR4_EIC2_MASK FSL_SRDSCR4_EIC2(0x1f)
+#define FSL_SRDSCR4_EIC3(x) (((x) & 0x1f) << 0)
+#define FSL_SRDSCR4_EIC3_MASK FSL_SRDSCR4_EIC3(0x1f)
+#define EIC_PCIE 0x13
+#define EIC_SGMII 0x04
+
#define SRDS1_MAX_LANES 4
static u32 serdes1_prtcl_map;
@@ -45,10 +63,13 @@ int is_serdes_configured(enum srds_prtcl prtcl)
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR;
+
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ u32 mask, val;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
@@ -61,4 +82,30 @@ void fsl_serdes_init(void)
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Init SERDES Receiver electrical idle detection control for PCIe */
+
+ /* Lane 0 is always PCIe 1 */
+ mask = FSL_SRDSCR3_EIC0_MASK;
+ val = FSL_SRDSCR3_EIC0(EIC_PCIE);
+
+ /* Lane 1 */
+ if ((serdes1_cfg_tbl[srds_cfg][1] == PCIE1) ||
+ (serdes1_cfg_tbl[srds_cfg][1] == PCIE2)) {
+ mask |= FSL_SRDSCR3_EIC1_MASK;
+ val |= FSL_SRDSCR3_EIC1(EIC_PCIE);
+ }
+
+ /* Handle lanes 0 & 1 */
+ clrsetbits_be32(&serdes->srdscr3, mask, val);
+
+ /* Handle lanes 2 & 3 */
+ if (srds_cfg == 0x6) {
+ mask = FSL_SRDSCR4_EIC2_MASK | FSL_SRDSCR4_EIC3_MASK;
+ val = FSL_SRDSCR4_EIC2(EIC_PCIE) | FSL_SRDSCR4_EIC3(EIC_PCIE);
+ clrsetbits_be32(&serdes->srdscr4, mask, val);
+ }
+
+ /* 100 ms delay */
+ udelay(100000);
}
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index c32c469..0529632 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -101,6 +101,7 @@
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -110,6 +111,7 @@
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -139,6 +141,7 @@
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -148,6 +151,7 @@
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -168,6 +172,7 @@
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -176,6 +181,7 @@
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -205,6 +211,7 @@
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -214,6 +221,7 @@
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
+#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 7b98e95..ab461b4 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -325,6 +325,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
+#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
+ temp32 = 0;
+ pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32);
+ temp32 &= ~0x03; /* Disable ASPM */
+ pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32);
+ udelay(1);
+#endif
if (pcie_cap == PCI_CAP_ID_EXP) {
pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
enabled = ltssm >= PCI_LTSSM_L0;
diff --git a/include/pci.h b/include/pci.h
index c6b264b..1284c42 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -306,6 +306,7 @@
#define PCI_DCR 0x54 /* PCIe Device Control Register */
#define PCI_DSR 0x56 /* PCIe Device Status Register */
#define PCI_LSR 0x5e /* PCIe Link Status Register */
+#define PCI_LCR 0x5c /* PCIe Link Control Register */
#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
#define PCI_LTSSM_L0 0x16 /* L0 state */
--
1.7.2.3
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