[U-Boot] [PATCH] corenet_ds: pick the middle value for all tested timing parameters

[Kumar Gala]

On Mar 5, 2011, at 10:13 AM, Kumar Gala wrote:

> From: York Sun <yorksun at freescale.com>
> 
> For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent.
> The best values should be picked up from the middle of all working
> combinations. This patch updates the table with confirmed values tested on
> Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s,
> 900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s,
> 1200MT/s, 1000MT/s.
> 
> Signed-off-by: York Sun <yorksun at freescale.com>
> ---
> board/freescale/corenet_ds/ddr.c |   58 ++++++++++++--------------------------
> 1 files changed, 18 insertions(+), 40 deletions(-)

applied

- k