[U-Boot] [PATCH 4/5] powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB

[Kumar Gala]

On Mar 6, 2011, at 10:17 PM, Kumar Gala wrote:

> From: Poonam Aggrwal <poonam.aggrwal at freescale.com>
> 
> Changed the following DDR timing parameters for 800Mt/s:
> tRRT    BL/2+1 to  BL/2
> tWWT    BL/2+1 to  BL/2
> tWRT    BL/2+1 to  BL/2
> tRWT    BL/2+1 to  BL/2
> REFINT  6500ns to  7800ns
> 
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal at freescale.com>
> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
> ---
> board/freescale/p1_p2_rdb/ddr.c |    4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)

applied to 85xx next

- k