[U-Boot] Coldfire 5235 flexbus.h

[Jate Sujjavanich]

So this simpler patch is appropriate.

--- u-boot-denx/arch/m68k/include/asm/coldfire/flexbus.h	2011-03-02 11:02:14.000000000 -0500
+++ u-boot/include/asm-m68k/coldfire/flexbus.h	2011-03-25 11:42:46.000000000 -0400
@@ -94,6 +94,12 @@
 #endif
 #define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
 
+#ifdef CONFIG_M5235
+#define FBCS_CSCR_SRWS(x)		(((x) & 0x3) << 14)
+#define FBCS_CSCR_IWS(x)		(((x) & 0xF) << 10)
+#define FBCS_CSCR_SWWS(x)		(((x) & 0x7) << 0)
+#endif
+
 #define FBCS_CSCR_SWS(x)		(((x) & 0x3F) << 26)
 #define FBCS_CSCR_SWS_MASK		(0x03FFFFFF)
 #define FBCS_CSCR_SWSEN			(0x00800000)

-----Original Message-----
From: Jin Zhengxiong-R64188 [mailto:R64188 at freescale.com] 
Sent: Tuesday, March 22, 2011 2:52 AM
To: Jate Sujjavanich; 'u-boot at lists.denx.de'
Subject: RE: Coldfire 5235 flexbus.h

> -----Original Message-----
> From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de] On
> Behalf Of Jate Sujjavanich
> Sent: Thursday, March 03, 2011 2:44 AM
> To: 'u-boot at lists.denx.de'
> Subject: [U-Boot] Coldfire 5235 flexbus.h
> 
> The defines in arch/m68k/include/coldfire/flexbus.h are not compatible with the
> 5235 processor. The registers in struct fbcs are different sizes from those in
> the 5235. Also, the defines are a little different.
> 
> This is what I have so far. Comments?
> 
> 
> 
> --- u-boot-denx/arch/m68k/include/asm/coldfire/flexbus.h    2011-03-02
> 11:02:14.000000000 -0500
> +++ u-boot/include/asm-m68k/coldfire/flexbus.h  2011-02-24 13:40:07.000000000 -
> 0500
> @@ -30,6 +30,57 @@
> * FlexBus Chip Selects (FBCS)
> *********************************************************************/
> 
> +#ifdef CONFIG_M5235
> +typedef struct fbcs {
 
[snip]

> +    u16 cscr7;
> +} fbcs_t;
> +#else

There are some different bit definition for the chip select module on all the ColdFire chips but the address is aligned for all the chips. Write to those reserved bit have no effect. Usually these configuration registers were initialized very only and the value write to them are defined by the platform with macro, So please try to hide the bit difference in the platform macro definition.  

[snip]
> +#ifdef CONFIG_M5235
> +#define FBCS_CSCR_SRWS(x)       (((x) & 0x3) << 14)
> +#define FBCS_CSCR_IWS(x)        (((x) & 0xF) << 10)
> +#define FBCS_CSCR_AA_ON         (1 << 8)
> +#define FBCS_CSCR_AA_OFF        (0 << 8)
> +#define FBCS_CSCR_PS_32         (0 << 6)
> +#define FBCS_CSCR_PS_16         (2 << 6)
> +#define FBCS_CSCR_PS_8          (1 << 6)
> +#define FBCS_CSCR_BEM_ON        (1 << 5)
> +#define FBCS_CSCR_BEM_OFF       (0 << 5)
> +#define FBCS_CSCR_BSTR_ON       (1 << 4)
> +#define FBCS_CSCR_BSTR_OFF      (0 << 4)
> +#define FBCS_CSCR_BSTW_ON       (1 << 3)
> +#define FBCS_CSCR_BSTW_OFF      (0 << 3)
> +#define FBCS_CSCR_SWWS(x)       (((x) & 0x7) << 0)
If the bit operation for the chip select module is needed, Please try to define it align with the common fbcs_t structure, Thanks.

Best Regards,
Jason


 
 
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