[U-Boot] [PATCH] powerpc/85xx: Add basic support for P1010RDB
Poonam Aggrwal
poonam.aggrwal at freescale.com
Wed May 4 19:23:19 CEST 2011
Boot methods supported: NOR Flash, NAND Flash, SPI Flash and SDCARD
This patch adds the following basic interfaces:
DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, NAND Flash
SPI Flash.
P1010RDB Overview
-----------------
1Gbyte DDR3 (on board DDR)
Local Bus (IFC):
32Mbyte 16bit NOR flash
32Mbyte SLC NAND Flash
64KB CPLD device(GPCM interface)
SPI Flash:
128 Mbit SPI Flash memory
SD/MMC:
connector to interface with the SD memory card
SATA:
1 internal SATA connect to 2.5. 160G SATA2 HDD
1 eSATA connector to rear panel
USB 2.0:
x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
eTSEC:
eTSEC1: Connected to RGMII PHY VSC8641XKO
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY VSC8221
eCAN:
Two DB-9 female connectors for Field bus interface
UART:
supports two UARTs up to 115200 bps for console
TDM:
2 FXS ports connected via an external SLIC to the TDM interface.
SLIC:
SPI SLIC
I2C:
Serial EEprom
Real time clock
256 Kbit M24256 I2C EEPROM
PCIe:
PCIe and mPCIe connectors.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal at freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh at freescale.com>
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
board/freescale/p1010rdb/Makefile | 52 ++
board/freescale/p1010rdb/ddr.c | 168 ++++++
board/freescale/p1010rdb/law.c | 35 ++
board/freescale/p1010rdb/p1010rdb.c | 334 +++++++++++
board/freescale/p1010rdb/tlb.c | 98 ++++
boards.cfg | 8 +
doc/README.p1010rdb | 259 +++++++++
include/configs/P1010RDB.h | 767 +++++++++++++++++++++++++
nand_spl/board/freescale/p1010rdb/Makefile | 142 +++++
nand_spl/board/freescale/p1010rdb/nand_boot.c | 119 ++++
10 files changed, 1982 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/p1010rdb/Makefile
create mode 100644 board/freescale/p1010rdb/ddr.c
create mode 100644 board/freescale/p1010rdb/law.c
create mode 100644 board/freescale/p1010rdb/p1010rdb.c
create mode 100644 board/freescale/p1010rdb/tlb.c
create mode 100644 doc/README.p1010rdb
create mode 100644 include/configs/P1010RDB.h
create mode 100644 nand_spl/board/freescale/p1010rdb/Makefile
create mode 100644 nand_spl/board/freescale/p1010rdb/nand_boot.c
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
new file mode 100644
index 0000000..1dcd490
--- /dev/null
+++ b/board/freescale/p1010rdb/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
new file mode 100644
index 0000000..f46f42a
--- /dev/null
+++ b/board/freescale/p1010rdb/ddr.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CONFIG_SYS_DRAM_SIZE 1024
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {800, 900, &ddr_cfg_regs_800},
+ {607, 700, &ddr_cfg_regs_667},
+ {0, 0, NULL}
+};
+
+unsigned long get_sdram_size(void)
+{
+ struct cpu_type *cpu;
+ phys_size_t ddr_size;
+
+ cpu = gd->cpu;
+ /* P1014 and it's derivatives support max 16it DDR width */
+ if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E)
+ ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
+ else
+ ddr_size = CONFIG_SYS_DRAM_SIZE;
+
+ return ddr_size;
+}
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+phys_size_t fixed_sdram(void)
+{
+ int i;
+ sys_info_t sysinfo;
+ char buf[32];
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ phys_size_t ddr_size;
+ ulong ddr_freq, ddr_freq_mhz;
+ struct cpu_type *cpu;
+
+#if defined(CONFIG_SYS_RAMBOOT)
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+#endif
+
+ ddr_freq = get_ddr_freq(0);
+ ddr_freq_mhz = ddr_freq / 1000000;
+
+ get_sys_info(&sysinfo);
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+ if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+ (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+ memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ break;
+ }
+ }
+
+ if (fixed_ddr_parm_0[i].max_freq == 0)
+ panic("Unsupported DDR data rate %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ cpu = gd->cpu;
+ /* P1014 and it's derivatives support max 16bit DDR width */
+ if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {
+ ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
+ ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1;
+ }
+ else {
+ ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
+ ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ }
+
+ ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
+ LAW_TRGT_IF_DDR_1) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+
+ return ddr_size;
+}
diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c
new file mode 100644
index 0000000..3ed77fc
--- /dev/null
+++ b/board/freescale/p1010rdb/law.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SDCARD
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
new file mode 100644
index 0000000..5d6b993
--- /dev/null
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <pci.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_ifc.h>
+#include <asm/fsl_pci.h>
+
+#ifndef CONFIG_SDCARD
+#include <hwconfig.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO4_PCIE_RESET_SET 0x08000000
+#define MUX_CPLD_CAN_UART 0x00
+#define MUX_CPLD_TDM 0x01
+#define MUX_CPLD_SPICS0_FLASH 0x00
+#define MUX_CPLD_SPICS0_SLIC 0x02
+
+#ifndef CONFIG_SDCARD
+struct cpld_data {
+ u8 cpld_ver; /* cpld revision */
+ u8 pcba_ver; /* pcb revision number */
+ u8 twindie_ddr3;
+ u8 res1[6];
+ u8 bank_sel; /* NOR Flash bank */
+ u8 res2[5];
+ u8 usb2_sel;
+ u8 res3[1];
+ u8 porsw_sel;
+ u8 tdm_can_sel;
+ u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
+ u8 por0; /* POR Options */
+ u8 por1; /* POR Options */
+ u8 por2; /* POR Options */
+ u8 por3; /* POR Options */
+};
+
+void cpld_show(void)
+{
+ volatile struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ printf("CPLD: V%x.%x PCBA: V%x.0\n",
+ in_8(&cpld_data->cpld_ver) & 0xF0,
+ in_8(&cpld_data->cpld_ver) & 0x0F,
+ in_8(&cpld_data->pcba_ver) & 0x0F);
+
+#ifdef CONFIG_DEBUG
+ printf("twindie_ddr =%x\n",
+ in_8(&cpld_data->twindie_ddr3));
+ printf("bank_sel =%x\n",
+ in_8(&cpld_data->bank_sel));
+ printf("usb2_sel =%x\n",
+ in_8(&cpld_data->usb2_sel));
+ printf("porsw_sel =%x\n",
+ in_8(&cpld_data->porsw_sel));
+ printf("tdm_can_sel =%x\n",
+ in_8(&cpld_data->tdm_can_sel));
+ printf("tdm_can_sel =%x\n",
+ in_8(&cpld_data->tdm_can_sel));
+ printf("spi_cs0_sel =%x\n",
+ in_8(&cpld_data->spi_cs0_sel));
+ printf("bcsr0 =%x\n",
+ in_8(&cpld_data->bcsr0));
+ printf("bcsr1 =%x\n",
+ in_8(&cpld_data->bcsr1));
+ printf("bcsr2 =%x\n",
+ in_8(&cpld_data->bcsr2));
+ printf("bcsr3 =%x\n",
+ in_8(&cpld_data->bcsr3));
+#endif
+}
+#endif
+
+int board_early_init_f (void)
+{
+ struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+
+#ifndef CONFIG_SDCARD
+ /* Clock configuration to access CPLD using IFC(GPCM) */
+ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+ setbits_be32(&ifc->ifc_ccr, IFC_CCR_CLK_DIV(15) | IFC_CCR_INV_CLK_EN);
+
+ cpld_show();
+#endif
+ /*
+ * Reset PCIe slots via GPIO4
+ */
+ setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
+ setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifndef CONFIG_SDCARD
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_16M, 1);
+
+ set_tlb(1, flashbase + 0x1000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif /* ifdef CONFIG_PCI */
+
+int checkboard (void)
+{
+ struct cpu_type *cpu;
+
+ cpu = gd->cpu;
+ printf ("Board: %sRDB\n", cpu->name);
+#ifdef CONFIG_PHYS_64BIT
+ puts ("(36-bit addrmap) \n");
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ struct cpu_type *cpu;
+ int num = 0;
+
+ cpu = gd->cpu;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ /* P1014 and it's derivatives do not support eTSEC3 */
+ if (cpu->soc_ver != SVR_P1014 && cpu->soc_ver != SVR_P1014_E) {
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ num++;
+ }
+#endif
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_del_flexcan(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "fsl,flexcan-v1.0")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
+
+void fdt_del_spi_flash(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "spansion,s25sl12801")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
+
+void fdt_del_spi_slic(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "zarlink,le88266")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
+
+void fdt_del_tdm(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "fsl,starlite-tdm")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+ struct cpu_type *cpu;
+
+ cpu = gd->cpu;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+#if defined(CONFIG_PCI)
+ FT_FSL_PCI_SETUP;
+#endif
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ /* P1014 and it's derivatives don't support CAN and eTSEC3 */
+ if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {
+ fdt_del_flexcan(blob);
+ fdt_del_node_and_alias(blob, "ethernet2");
+ }
+#ifndef CONFIG_SDCARD
+ /* In case of SPI Boot SPI SLIC will not be available */
+#ifdef CONFIG_SPIFLASH
+ fdt_del_spi_slic(blob);
+#endif
+ if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
+ printf("fdt CAN");
+ fdt_del_tdm(blob);
+ fdt_del_spi_slic(blob);
+ }
+#ifdef CONFIG_NAND_U_BOOT
+ else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
+ printf("fdt TDM");
+ fdt_del_flexcan(blob);
+ fdt_del_spi_flash(blob);
+ }
+#endif
+#endif
+}
+#endif
+
+#ifndef CONFIG_SDCARD
+int misc_init_r(void)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
+ MPC85xx_PMUXCR_CAN1_UART |
+ MPC85xx_PMUXCR_CAN2_TDM |
+ MPC85xx_PMUXCR_CAN2_UART);
+ out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+ }
+#ifdef CONFIG_NAND_U_BOOT
+ if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
+ printf("TDM");
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
+ MPC85xx_PMUXCR_CAN1_UART);
+ setbits_be32(&gur->pmuxcr,MPC85xx_PMUXCR_CAN2_TDM |
+ MPC85xx_PMUXCR_CAN1_TDM);
+ clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
+ setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
+ out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
+ out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+ }
+#endif
+ return 0;
+}
+#endif
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
new file mode 100644
index 0000000..b1343fd
--- /dev/null
+++ b/board/freescale/p1010rdb/tlb.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SDCARD
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_16M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_16M, 1),
+#endif
+
+#ifdef CONFIG_PCI
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+#ifndef CONFIG_SDCARD
+ /* *I*G - Board CPLD */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index fde9913..4ca3142 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -510,6 +510,14 @@ MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freesca
MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS
MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT
MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND
+P1010RDB_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB
+P1010RDB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT
+P1010RDB_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND
+P1010RDB_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND
+P1010RDB_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SDCARD
+P1010RDB_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH
+P1010RDB_36BIT_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SDCARD
+P1010RDB_36BIT_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH
P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB
P1011RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT
P1011RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SDCARD
diff --git a/doc/README.p1010rdb b/doc/README.p1010rdb
new file mode 100644
index 0000000..2a84eeb
--- /dev/null
+++ b/doc/README.p1010rdb
@@ -0,0 +1,259 @@
+Overview
+--------
+P1010 is a Low End Dual core platform supporting the P1010 processor of QorIQ
+series.
+It also supports P1014 RDB personality.
+
+P1010 Vs P1014
+--------------
+Interface P1010 P1014
+DDR data width 32bit 16bit
+Flexcan Y N
+Trusted Boot Y N
+Ethernet i/fs eTSEC1 2 and 3 eTSEC1 and 2
+
+How to select P1014 personality on P1010RDB:
+ Change SW2[8] to ON.
+
+P1010RDB Overview
+-----------------
+1Gbyte DDR3 (on board DDR)
+Local Bus (IFC):
+ 32Mbyte 16bit NOR flash
+ 32Mbyte SLC NAND Flash
+ 64KB CPLD device(GPCM interface)
+SPI Flash:
+ 128 Mbit SPI Flash memory
+SD/MMC:
+ connector to interface with the SD memory card
+SATA:
+ 1 internal SATA connect to 2.5. 160G SATA2 HDD
+ 1 eSATA connector to rear panel
+USB 2.0:
+ x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
+ x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
+eTSEC:
+ eTSEC1: Connected to RGMII PHY VSC8641XKO
+ eTSEC2: Connected to SGMII PHY VSC8221
+ eTSEC3: Connected to SGMII PHY VSC8221
+eCAN:
+ Two DB-9 female connectors for Field bus interface
+UART:
+ supports two UARTs up to 115200 bps for console
+TDM:
+ 2 FXS ports connected via an external SLIC to the TDM interface.
+SLIC:
+ SPI SLIC
+I2C:
+ Serial EEprom
+ Real time clock
+ 256 Kbit M24256 I2C EEPROM
+PCIe:
+ PCIe and mPCIe connectors.
+
+Highest Frequency Supported:
+----------------------------
+Core/CCB/DDR data rate
+-> 800MHz/400MHz/800MT/s
+
+Building U-boot
+---------------
+Boot Methods supported:
+
+1. Boot From NOR Flash
+ # make P1010RDB_NOR
+ # make P1010RDB_36BIT_NOR
+
+2. Boot from SD card
+ # make P1010RDB_SDCARD
+ # make P1010RDB_36BIT_SDCARD
+
+3. Boot from SPI Flash
+ # make P1010RDB_SPIFLASH
+ # make P1010RDB_36BIT_SPIFLASH
+
+4. Boot from NAND flash
+ # make P1010RDB_NAND
+ # make P1010RDB_36BIT_NAND
+
+Memory Map
+----------
+
+Address Start Address End Memory type Attributes
+0x0000_0000 0x3fff_ffff DDR 1G cacheable
+0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
+0xee00_0000 0xefff_ffff NOR Flash 128MB non-cacheable
+0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
+0xffa0_0000 0xffaf_ffff NAND Flash 1M non-cacheable
+0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
+0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
+0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+
+Primary NOR Flash boot bank location:
+--------------------------------------
+0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB
+
+Alternate NOR Flash Boot bank location:
+---------------------------------------
+0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB
+
+36bit Memory Map on P1010RDB
+----------------------------
+Address Start Address End Memory type Attributes
+0x00000_0000 0x03fff_ffff DDR 1G Cacheable
+0xa0000_0000 0x0dfff_ffff PCI Express Mem 1G non-cacheable
+0xfee00_0000 0xfefff_ffff NOR Flash 128MB non-cacheable
+0xfffc2_0000 0xfffc5_ffff PCI IO range 256K non-cacheable
+0xfffa0_0000 0xfffaf_ffff NAND Flash 1M cacheable
+0xfffb0_0000 0xfffbf_ffff Board CPLD 1M non-cacheable
+0xfffd0_0000 0xfffd0_3fff L1 for Stack 16K Cacheable TLB0
+0xfffe0_0000 0xfffef_ffff CCSR 1M non-cacheable
+
+Switch settings on P1010RDB:
+----------------------------
+NOR Boot
+---------
+SW1.1~SW1.8 OFF,OFF,OFF,OFF,ON,OFF,ON,OFF
+SW2.1~SW2.8 ON,ON,OFF,ON,ON,OFF,OFF,OFF
+SW3.1~SW3.4 OFF,ON,ON,ON
+SW4.1~SW4.4 ON,ON,ON,ON
+SW6.1~SW6.4 ON,OFF,OFF,OFF
+
+NAND Boot
+---------
+SW1.1~SW1.8 OFF,OFF,OFF,OFF,ON,OFF,ON,OFF
+SW2.1~SW2.8 ON,ON,OFF,ON,ON,OFF,OFF,OFF
+SW3.1~SW3.4 OFF,ON,ON,ON
+SW4.1~SW4.4 ON,OFF,OFF,OFF
+SW6.1~SW6.4 ON,OFF,OFF,ON
+Note: Please make sure to mount jumpers across J11 and J12 to disable ECC. ECC
+is not supported in NAND boot currently.
+
+SD Card boot
+------------
+SW1.1~SW1.8 OFF,OFF,OFF,OFF,ON,OFF,ON,OFF
+SW2.1~SW2.8 ON,ON,OFF,ON,ON,OFF,OFF,OFF
+SW3.1~SW3.4 OFF,ON,ON,ON
+SW4.1~SW4.4 OFF,ON,ON,ON
+SW6.1~SW6.4 ON,OFF,ON,OFF
+
+SPI Flash boot
+--------------
+SW1.1~SW1.8 OFF,OFF,OFF,OFF,ON,OFF,ON,OFF
+SW2.1~SW2.8 ON,ON,OFF,ON,ON,OFF,OFF,OFF
+SW3.1~SW3.4 OFF,ON,ON,ON
+SW4.1~SW4.4 OFF,ON,ON,OFF
+SW6.1~SW6.4 ON,OFF,OFF,ON
+
+Bus Selection:
+
+CPLD on P1010RDB
+----------------
+CPLD is connected through IFC-GPCM at address 0xffb00000.
+
+Multiplexing on P1010RDB
+------------------------
+P1010 SOC has various interfaces multiplexed, hence only limited interfaces are
+available at one time.
+Proper Board Design and software design is required to work with the multiplexed
+scenarios.
+Majorly the multiplexing on P1010 is
+1. IFC(some signals)/SDHC/USB-ULPI
+2. CAN/TDM
+3. Use of TDM also restricts UART1 to data signals only (no flow control).
+4. There is only one Chipselect in P1010 eSPI Controller which has to be shared
+ between SPI Flash and SPI SLIC.
+
+To accomodate (1) the above P1010RDB has a switch SW6 which allows the user to
+select the desired bus (IFC /SDHC /USB-ULPI)
+
+|-----------------------------------------------------------|
+|Interface SW6.1 SW6.2 SW6.3 SW6.4 LED |
+|-----------------------------------------------------------|
+|USB-ULPI OFF ON ON X D9 |
+|SDHC ON OFF ON X D10 |
+|IFC CS0=NOR CS1=NAND ON OFF OFF OFF D8 |
+|IFC CS0=NAND CS1=NOR ON OFF OFF ON D8 |
+------------------------------------------------------------
+
+For (2),(3)and (4)
+the muxing is controlled by register writes to the CPLD. Pleaste note that
+CPLD is itself accessible through IFC hence CPLD will only be available
+when IFC is selected through SW6.
+
+Considering the above and different boot locations the u-boot has been
+designed to create the following mux picture of the System.
+
+|---------------------------------------------------------------------------|
+|Romloc SW6 SD USB NOR NAND CPLD SPI TDM CAN |
+| ULPI Flash SLIC |
+|---------------------------------------------------------------------------|
+|SD SD Y N N N N Y N N |
+|NOR IFC-CS0 N N Y Y Y conf conf conf|
+| NOR |
+|NAND IFC-CS0 N N Y Y Y conf conf conf|
+| NAND |
+|SPI IFC-CS0 N N Y Y Y Y N conf|
+| NOR |
+|---------------------------------------------------------------------------|
+
+The above picture wll be consistent throughout u-boot and Linux.`
+
+The u-boot provides a hwconfig interface to the user to select CAN/TDM
+ hwconfig usage to select TDM or CAN:
+ setenv hwconfig "fsl_p1010mux:tdm_can=can"
+ setenv hwconfig "fsl_p1010mux:tdm_can=tdm"
+
+Note:
+1. When TDM is selected SLIC also gets enabled by software.
+2. u-boot also fixes up the device tree according to the user selection to make
+ sure that the changes also get reflected in Linux.
+
+Switch settings to boot from the NOR flash banks
+------------------------------------------------
+SW1[8]= ON default NOR Flash bank
+SW1[8]= OFF Alternate NOR Flash bank
+
+Flashing Images
+---------------
+To place a new u-boot image in the alternate flash bank and then reset with that
+ new image temporarily, use this:
+ tftp 1000000 u-boot.bin
+ erase ef780000 ef7fffff
+ cp.b 1000000 ef780000 80000
+
+Now to boot from the alternate bank change the SW4[8] from 0 to 1.
+
+To program the image in the boot flash bank:
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase eff80000 ffffffff
+ cp.b 1000000 eff80000 80000
+
+Using the Device Tree Source File
+---------------------------------
+ To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb p1010rdb.dts > p1010rdb.dtb
+./scripts/dtc/dtc -I dts -O dtb -R 0x0008 -p 0x1000
+ arch/powerpc/boot/dts/p1010rdb.dts > p1010rdb.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/p1010rdb.dts
+36bit dts file for p1010rdb is
+ linux-2.6/arch/powerpc/boot/dts/p1010rdb_36b.dts
+
+Building and Booting Linux
+--------------------------
+Linux can be compiled using arch/powerpc/configs/mpc85xx_defconfig
+
+Place a linux uImage in the TFTP disk area.
+
+ tftp 1000000 uImage.p1010rdb
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp c00000 p1010rdb.dtb
+ bootm 1000000 2000000 c00000
+
+For 36bit uImage, select Large Address Space via menuconfig.
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
new file mode 100644
index 0000000..bb20566
--- /dev/null
+++ b/include/configs/P1010RDB.h
@@ -0,0 +1,767 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P010 RDB board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+#ifdef CONFIG_P1010RDB
+#define CONFIG_P1010
+#define CONFIG_NAND_FSL_IFC
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_TEXT_BASE 0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_TEXT_BASE 0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+
+#ifdef CONFIG_NAND /* NAND Boot */
+#define CONFIG_RAMBOOT_NAND
+#define CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
+#else
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#endif /* CONFIG_NAND_SPL */
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE /* BOOKE */
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
+
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+
+#define CONFIG_E1000 /* E1000 pci Ethernet card*/
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
+#endif
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_TSEC_ENET
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
+#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
+
+#ifndef CONFIG_SDCARD
+#define CONFIG_MISC_INIT_R
+#endif
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x1fffffff
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_sdram_size(void);
+#endif
+#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+
+/* DDR3 Controller Settings */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
+#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
+#define CONFIG_SYS_DDR_RCW_1 0x00000000
+#define CONFIG_SYS_DDR_RCW_2 0x00000000
+#define CONFIG_SYS_DDR_CONTROL 0x47040000 /* Type = DDR3 */
+#define CONFIG_SYS_DDR_CONTROL_2 0x04401010
+#define CONFIG_SYS_DDR_TIMING_4 0x00000001
+#define CONFIG_SYS_DDR_TIMING_5 0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
+#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644
+#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
+#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
+#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
+#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
+
+/* settings for DDR3 at 667MT/s */
+#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
+#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
+#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
+#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
+#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
+#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
+#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
+
+/* "Don't relocate CCSRBAR while in NAND_SPL." */
+#if defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_DEFAULT
+#else
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
+#endif
+ /* CCSRBAR */
+#endif /* CONFIG_NAND_SPL */
+
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
+ /* CONFIG_SYS_IMMR */
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
+ * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
+ * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
+ *
+ * Localbus non-cacheable
+ * 0xffa0_0000 0xffaf_ffff NAND Flash 1M non-cacheable
+ * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
+ * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
+ * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+ */
+
+/* In case of SD card boot, IFC interface is not available because of muxing */
+#ifdef CONFIG_SDCARD
+#define CONFIG_SYS_NO_FLASH
+#else
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+#define CONFIG_SYS_FLASH_BASE 0xee000000
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5)
+#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
+ FTIM1_NOR_TRAD_NOR(0x0f)
+#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWP(0x1c)
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+/* CFI for NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* NAND Flash on IFC */
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
+ | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
+ | CSOR_NAND_PB(32)) /* Pages Per Block = 32 */
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
+
+/* NAND Flash Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
+ FTIM0_NAND_TWP(0x0C) | \
+ FTIM0_NAND_TWCHT(0x04) | \
+ FTIM0_NAND_TWH(0x05)
+#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
+ FTIM1_NAND_TWBE(0x1d) | \
+ FTIM1_NAND_TRR(0x07) | \
+ FTIM1_NAND_TRP(0x0c)
+#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
+ FTIM2_NAND_TREH(0x05) | \
+ FTIM2_NAND_TWHRE(0x0f)
+#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+
+/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+
+/* NAND boot: 8K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE 0x2000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE 0xffb00000
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
+#else
+#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#endif
+
+#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3 0x0
+/* CPLD Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3 0x0
+#endif /* CONFIG_SDCARD */
+
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
+ defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
+ - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/* I2C EEPROM */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM 1
+
+/* RTC */
+#define CONFIG_RTC_PT7C4338
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+#define CONFIG_CMD_I2C
+
+/*
+ * SPI interface will not be available in case of NAND boot SPI CS0 will be
+ * used for SLIC
+ */
+#ifndef CONFIG_NAND_U_BOOT
+/* eSPI - Enhanced SPI */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+
+#define TSEC1_PHY_ADDR 1
+#define TSEC2_PHY_ADDR 0
+#define TSEC3_PHY_ADDR 2
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+
+/* TBI PHY configuration for SGMII mode */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_ANEG_ENABLE \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
+#endif /* CONFIG_TSEC_ENET */
+
+
+/* SATA */
+#define CONFIG_FSL_SATA
+#define CONFIG_LIBATA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_CMD_SATA
+#define CONFIG_LBA48
+#endif /* #ifdef CONFIG_FSL_SATA */
+
+/* SD interface will only be available in case of SD boot */
+#ifdef CONFIG_SDCARD
+#define CONFIG_MMC
+#define CONFIG_DEF_HWCONFIG esdhc
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_NAND_U_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
+#else
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#endif
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR 0xfff80000
+#else
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
+ || defined(CONFIG_FSL_SATA)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+#define CONFIG_HOSTNAME P1010RDB
+#define CONFIG_ROOTPATH /opt/nfsroot
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=" MK_STR(CONFIG_DEF_HWCONFIG) "\0" \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "loadaddr=1000000\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=rootfs.ext2.gz.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=p1010rdb.dtb\0" \
+ "bdev=sda1\0" \
+ "usb_phy_type=utmi\0" \
+ "usb_dr_mode=host\0" \
+ "othbootargs=ramdisk_size=600000\0" \
+ "usbfatboot=setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs; " \
+ "usb start;" \
+ "fatload usb 0:2 $loadaddr $bootfile;" \
+ "fatload usb 0:2 $fdtaddr $fdtfile;" \
+ "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
+ "usbext2boot=setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs; " \
+ "usb start;" \
+ "ext2load usb 0:4 $loadaddr $bootfile;" \
+ "ext2load usb 0:4 $fdtaddr $fdtfile;" \
+ "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs; " \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile
new file mode 100644
index 0000000..f53f397
--- /dev/null
+++ b/nand_spl/board/freescale/p1010rdb/Makefile
@@ -0,0 +1,142 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# Copyright 2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+NAND_SPL := y
+CONFIG_SYS_TEXT_BASE_SPL := 0xff800000
+PAD_TO := 0xff802000
+
+include $(TOPDIR)/config.mk
+
+nandobj := $(OBJTREE)/nand_spl/
+
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \
+ $(LDFLAGS_FINAL)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
+SOBJS = start.o resetvec.o ticks.o
+COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+ nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(nandobj)board/$(BOARDDIR)
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+ @rm -f $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+ @rm -f $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
+
+$(obj)cpu_init_nand.c:
+ @rm -f $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+ @rm -f $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+ @rm -f $(obj)law.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_ifc.c:
+ @rm -f $(obj)nand_boot_fsl_ifc.c
+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_ifc.c \
+ $(obj)nand_boot_fsl_ifc.c
+
+$(obj)ns16550.c:
+ @rm -f $(obj)ns16550.c
+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)resetvec.S:
+ @rm -f $(obj)resetvec.S
+ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+
+$(obj)fixed_ivor.S:
+ @rm -f $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+ @rm -f $(obj)start.S
+ ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
+
+$(obj)ticks.S:
+ @rm -f $(obj)ticks.S
+ ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
+
+$(obj)tlb.c:
+ @rm -f $(obj)tlb.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+ @rm -f $(obj)tlb_table.c
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)nand_boot.c:
+ @rm -f $(obj)nand_boot.c
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+endif
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c
new file mode 100644
index 0000000..f0de279
--- /dev/null
+++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+
+#define udelay(x) {int i, j; for (i = 0; i < x; i++) for (j = 0; j < 10000; j++); }
+
+unsigned long bus_clk;
+
+void sdram_init(void)
+{
+ volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+
+ out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+ out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+ out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800);
+ out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800);
+ out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800);
+ out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800);
+
+ out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
+ out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800);
+ out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800);
+
+ out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800);
+ out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+ out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800);
+
+ out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
+ out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
+ out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
+ out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL);
+
+ /* Set, but do not enable the memory */
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
+
+ asm volatile("sync;isync");
+ udelay(500);
+
+ /* Let the controller go */
+ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+ set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* Initialize the DDR3 */
+ sdram_init();
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
+ CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+unsigned long get_tbclk(void)
+{
+ return (bus_clk + 4UL)/8UL;
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
--
1.6.5.6
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