[U-Boot] [PATCH v3 08/10] armv7: adapt omap4 to the new cache maintenance framework

[Aneesh V]

adapt omap4 to the new layered cache maintenance framework

Signed-off-by: Aneesh V <aneesh at ti.com>
---
V2:
 * Changes for the function pointer to weakly linked change
---
 arch/arm/cpu/armv7/omap4/lowlevel_init.S    |   18 ++++++++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h |    1 -
 include/configs/omap4_panda.h               |    8 +++++---
 include/configs/omap4_sdp4430.h             |    8 +++++---
 4 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
index 026dfa4..5e6c16f 100644
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -45,3 +45,21 @@ lowlevel_init:
 	 */
 	bl	s_init
 	pop	{ip, pc}
+
+set_pl310_ctrl_reg:
+	PUSH	{r4-r11, lr}	@ save registers - ROM code may pollute
+				@ our registers
+	LDR	r12, =0x102	@ Set PL310 control register - value in R0
+	.word	0xe1600070	@ SMC #0 - hand assembled because -march=armv5
+				@ call ROM Code API to set control register
+	POP	{r4-r11, pc}
+
+.globl v7_outer_cache_enable
+v7_outer_cache_enable:
+	MOV	r0, #1
+	B	set_pl310_ctrl_reg
+
+.globl v7_outer_cache_disable
+v7_outer_cache_disable:
+	MOV	r0, #0
+	B	set_pl310_ctrl_reg
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4813e9e..017f216 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -31,7 +31,6 @@ struct omap_sysinfo {
 void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
-void invalidate_dcache(u32);
 void set_muxconf_regs(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 12daebc..9acd340 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -45,9 +45,6 @@
 #define CONFIG_DISPLAY_CPUINFO		1
 #define CONFIG_DISPLAY_BOARDINFO	1
 
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_NO_L2CACHE			1
-
 /* Clock Defines */
 #define V_OSCK			38400000	/* Clock output from T2 */
 #define V_SCLK                   V_OSCK
@@ -236,4 +233,9 @@
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 
+#ifndef CONFIG_SYS_NO_L2CACHE
+#define CONFIG_SYS_L2_PL310		1
+#define CONFIG_SYS_PL310_BASE	0x48242000
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 673cd5c..0fd08b3 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -46,9 +46,6 @@
 #define CONFIG_DISPLAY_CPUINFO		1
 #define CONFIG_DISPLAY_BOARDINFO	1
 
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_NO_L2CACHE			1
-
 /* Clock Defines */
 #define V_OSCK			38400000	/* Clock output from T2 */
 #define V_SCLK                   V_OSCK
@@ -242,4 +239,9 @@
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 
+#ifndef CONFIG_SYS_NO_L2CACHE
+#define CONFIG_SYS_L2_PL310		1
+#define CONFIG_SYS_PL310_BASE	0x48242000
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.7.0.4