[U-Boot] [PATCH v3 3/4] MX5: Introduce a function for setting the chip select size
Wolfgang Denk
wd at denx.de
Thu May 19 21:02:25 CEST 2011
Dear Fabio Estevam,
In message <1305751670-30808-3-git-send-email-fabio.estevam at freescale.com> you wrote:
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
> arch/arm/cpu/armv7/mx5/soc.c | 30 +++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-mx5/imx-regs.h | 5 ++++
> arch/arm/include/asm/arch-mx5/sys_proto.h | 2 +-
> 3 files changed, 36 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
> index 40b8b56..e599df8 100644
> --- a/arch/arm/cpu/armv7/mx5/soc.c
> +++ b/arch/arm/cpu/armv7/mx5/soc.c
> @@ -163,6 +163,36 @@ int cpu_mmc_init(bd_t *bis)
> #endif
> }
>
> +void set_chipselect_size(int const cs_size)
> +{
> + unsigned int reg;
> + struct iomuxc *iomuxc_regs = (struct weim *)IOMUXC_BASE_ADDR;
> + reg = readl(&iomuxc_regs->gpr1);
> +
> + switch (cs_size) {
> + case CS0_128:
> + reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
> + reg |= 0x5;
> + break;
> + case CS0_64M_CS1_64M:
> + reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
> + reg |= 0x1B;
> + break;
> + case CS0_64M_CS1_32M_CS2_32M:
> + reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
> + reg |= 0x4B;
> + break;
> + case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
> + reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
> + reg |= 0x249;
> + break;
> + default:
> + printf("Unknown chip select size\n");
In cases like this, please _always_ print _what_ the unknown chip size
was. Please fix.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Hacking's just another word for nothing left to kludge.
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