[U-Boot] [PATCH] ARM: i.MX51: Config option to disable PLL1

[Stefano Babic]

On 05/26/2011 07:00 PM, David Jander wrote:
> i.MX51 PLL1 seems to have stability problems. It is advised to not use it,
> although it is unclear whether all boards and/or chip revisions have this
> problem. Using PLL2 for the core and DDR2 seems to fix the problem.
> No official errata yet.
> 

Hi David,

do you get some info from Freescale's FAE ? Is this issue strictly
related to the processor or can be board related ?

I hope someone from Freescale can help us to understand this issue.

> Signed-off-by: David Jander <david at protonic.nl>
> ---
>  arch/arm/cpu/armv7/mx5/lowlevel_init.S |   16 ++++++++++++++++
>  1 files changed, 16 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> index 96ebfe2..e1d6c35 100644
> --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> @@ -153,7 +153,11 @@
>  	mov r1, #0x4
>  	str r1, [r0, #CLKCTL_CCSR]
>  
> +#if defined(CONFIG_MX51_AVOID_PLL1)

If you add a new CONFIG_, you must document it in the README file.

Rather I cannot get a better feedback, I do not know this issue on the
i.MX51. As you reported, it seems still unclear what happens.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================