[U-Boot] [PATCH] PXA: Drop csb226 and innokom boards (unmaintained)
Robert Schwebel
r.schwebel at pengutronix.de
Thu Nov 3 17:29:39 CET 2011
On Thu, Nov 03, 2011 at 01:06:12AM +0100, Marek Vasut wrote:
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> Cc: Robert Schwebel <robert at schwebel.de>
> Cc: Albert ARIBAUD <albert.u.boot at aribaud.net>
Acked-by: Robert Schwebel <r.schwebel at pengutronix.de>
> ---
> MAINTAINERS | 5 -
> board/csb226/Makefile | 43 ----
> board/csb226/csb226.c | 166 ---------------
> board/csb226/flash.c | 368 --------------------------------
> board/innokom/Makefile | 43 ----
> board/innokom/flash.c | 421 -------------------------------------
> board/innokom/innokom.c | 190 -----------------
> boards.cfg | 2 -
> include/configs/csb226.h | 506 --------------------------------------------
> include/configs/innokom.h | 507 ---------------------------------------------
> 10 files changed, 0 insertions(+), 2251 deletions(-)
> delete mode 100644 board/csb226/Makefile
> delete mode 100644 board/csb226/csb226.c
> delete mode 100644 board/csb226/flash.c
> delete mode 100644 board/innokom/Makefile
> delete mode 100644 board/innokom/flash.c
> delete mode 100644 board/innokom/innokom.c
> delete mode 100644 include/configs/csb226.h
> delete mode 100644 include/configs/innokom.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 21d1fef..0a85df7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -812,11 +812,6 @@ Heiko Schocher <hs at denx.de>
> magnesium i.MX27
> mgcoge3un ARM926EJS (Kirkwood SoC)
>
> -Robert Schwebel <r.schwebel at pengutronix.de>
> -
> - csb226 xscale/pxa
> - innokom xscale/pxa
> -
> Michael Schwingen <michael at schwingen.org>
>
> actux1 xscale/ixp
> diff --git a/board/csb226/Makefile b/board/csb226/Makefile
> deleted file mode 100644
> index 6fe9bec..0000000
> --- a/board/csb226/Makefile
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -#
> -# (C) Copyright 2000-2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# See file CREDITS for list of people who contributed to this
> -# project.
> -#
> -# This program is free software; you can redistribute it and/or
> -# modify it under the terms of the GNU General Public License as
> -# published by the Free Software Foundation; either version 2 of
> -# the License, or (at your option) any later version.
> -#
> -# This program is distributed in the hope that it will be useful,
> -# but WITHOUT ANY WARRANTY; without even the implied warranty of
> -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> -# GNU General Public License for more details.
> -#
> -# You should have received a copy of the GNU General Public License
> -# along with this program; if not, write to the Free Software
> -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> -# MA 02111-1307 USA
> -#
> -
> -include $(TOPDIR)/config.mk
> -
> -LIB = $(obj)lib$(BOARD).o
> -
> -COBJS := csb226.o flash.o
> -
> -SRCS := $(COBJS:.o=.c)
> -OBJS := $(addprefix $(obj),$(COBJS))
> -
> -$(LIB): $(obj).depend $(OBJS)
> - $(call cmd_link_o_target, $(OBJS))
> -
> -#########################################################################
> -
> -# defines $(obj).depend target
> -include $(SRCTREE)/rules.mk
> -
> -sinclude $(obj).depend
> -
> -#########################################################################
> diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
> deleted file mode 100644
> index dd29e62..0000000
> --- a/board/csb226/csb226.c
> +++ /dev/null
> @@ -1,166 +0,0 @@
> -/*
> - * (C) Copyright 2002
> - * Robert Schwebel, Pengutronix, r.schwebel at pengutronix.de
> - * Kyle Harris, Nexus Technologies, Inc., kharris at nexus-tech.net
> - * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger at sysgo.de
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#include <common.h>
> -#include <netdev.h>
> -#include <asm/arch/pxa-regs.h>
> -#include <asm/io.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#ifdef CONFIG_SHOW_BOOT_PROGRESS
> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
> -#else
> -# define SHOW_BOOT_PROGRESS(arg)
> -#endif
> -
> -/**
> - * misc_init_r: - misc initialisation routines
> - */
> -
> -int misc_init_r(void)
> -{
> -#if 0
> - uchar *str;
> -
> - /* determine if the software update key is pressed during startup */
> - /* not ported yet... */
> - if (GPLR0 & 0x00000800) {
> - printf("using bootcmd_normal (sw-update button not pressed)\n");
> - str = getenv("bootcmd_normal");
> - } else {
> - printf("using bootcmd_update (sw-update button pressed)\n");
> - str = getenv("bootcmd_update");
> - }
> -
> - setenv("bootcmd",str);
> -#endif
> - return 0;
> -}
> -
> -
> -/**
> - * board_init: - setup some data structures
> - *
> - * @return: 0 in case of success
> - */
> -
> -int board_init (void)
> -{
> - /* We have RAM, disable cache */
> - dcache_disable();
> - icache_disable();
> -
> - /* arch number of CSB226 board */
> - gd->bd->bi_arch_number = MACH_TYPE_CSB226;
> -
> - /* adress of boot parameters */
> - gd->bd->bi_boot_params = 0xa0000100;
> -
> - return 0;
> -}
> -
> -
> -extern void pxa_dram_init(void);
> -int dram_init(void)
> -{
> - pxa_dram_init();
> - gd->ram_size = PHYS_SDRAM_1_SIZE;
> - return 0;
> -}
> -
> -void dram_init_banksize(void)
> -{
> - gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> -}
> -
> -/**
> - * csb226_set_led: - switch LEDs on or off
> - *
> - * @param led: LED to switch (0,1,2)
> - * @param state: switch on (1) or off (0)
> - */
> -
> -void csb226_set_led(int led, int state)
> -{
> - switch(led) {
> -
> - case 0: if (state==1) {
> - writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
> - } else if (state==0) {
> - writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
> - }
> - break;
> -
> - case 1: if (state==1) {
> - writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
> - } else if (state==0) {
> - writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
> - }
> - break;
> -
> - case 2: if (state==1) {
> - writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
> - } else if (state==0) {
> - writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
> - }
> - break;
> - }
> -
> - return;
> -}
> -
> -
> -/**
> - * show_boot_progress: - indicate state of the boot process
> - *
> - * @param status: Status number - see README for details.
> - *
> - * The CSB226 does only have 3 LEDs, so we switch them on at the most
> - * important states (1, 5, 15).
> - */
> -
> -void show_boot_progress (int status)
> -{
> - switch(status) {
> - case 1: csb226_set_led(0,1); break;
> - case 5: csb226_set_led(1,1); break;
> - case 15: csb226_set_led(2,1); break;
> - }
> -
> - return;
> -}
> -
> -#ifdef CONFIG_CMD_NET
> -int board_eth_init(bd_t *bis)
> -{
> - int rc = 0;
> -#ifdef CONFIG_CS8900
> - rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
> -#endif
> - return rc;
> -}
> -#endif
> diff --git a/board/csb226/flash.c b/board/csb226/flash.c
> deleted file mode 100644
> index e103470..0000000
> --- a/board/csb226/flash.c
> +++ /dev/null
> @@ -1,368 +0,0 @@
> -/*
> - * (C) Copyright 2002
> - * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
> - *
> - * (C) Copyright 2002
> - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> - * Marius Groeger <mgroeger at sysgo.de>
> - *
> - * (C) Copyright 2002
> - * Robert Schwebel, Pengutronix, <r.schwebel at pengutronix.de>
> - *
> - * (C) Copyright 2003 (2 x 16 bit Flash bank patches)
> - * Rolf Peukert, IMMS gGmbH, <rolf.peukert at imms.de>
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#include <common.h>
> -#include <asm/arch/pxa-regs.h>
> -
> -#define FLASH_BANK_SIZE 0x02000000
> -#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */
> -
> -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
> -
> -
> -/**
> - * flash_init: - initialize data structures for flash chips
> - *
> - * @return: size of the flash
> - */
> -
> -ulong flash_init(void)
> -{
> - int i, j;
> - ulong size = 0;
> -
> - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
> - ulong flashbase = 0;
> - flash_info[i].flash_id =
> - (INTEL_MANUFACT & FLASH_VENDMASK) |
> - (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
> - flash_info[i].size = FLASH_BANK_SIZE;
> - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
> - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
> -
> - switch (i) {
> - case 0:
> - flashbase = PHYS_FLASH_1;
> - break;
> - default:
> - panic("configured too many flash banks!\n");
> - break;
> - }
> - for (j = 0; j < flash_info[i].sector_count; j++) {
> - flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
> - }
> - size += flash_info[i].size;
> - }
> -
> - /* Protect monitor and environment sectors */
> - flash_protect(FLAG_PROTECT_SET,
> - CONFIG_SYS_FLASH_BASE,
> - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
> - &flash_info[0]);
> -
> - flash_protect(FLAG_PROTECT_SET,
> - CONFIG_ENV_ADDR,
> - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
> - &flash_info[0]);
> -
> - return size;
> -}
> -
> -
> -/**
> - * flash_print_info: - print information about the flash situation
> - */
> -
> -void flash_print_info (flash_info_t *info)
> -{
> - int i, j;
> -
> - for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
> -
> - switch (info->flash_id & FLASH_VENDMASK) {
> - case (INTEL_MANUFACT & FLASH_VENDMASK):
> - printf ("Intel: ");
> - break;
> - default:
> - printf ("Unknown Vendor ");
> - break;
> - }
> -
> - switch (info->flash_id & FLASH_TYPEMASK) {
> - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
> - printf("28F128J3 (128Mbit)\n");
> - break;
> - default:
> - printf("Unknown Chip Type\n");
> - return;
> - }
> -
> - printf(" Size: %ld MB in %d Sectors\n",
> - info->size >> 20, info->sector_count);
> -
> - printf(" Sector Start Addresses:");
> - for (i = 0; i < info->sector_count; i++) {
> - if ((i % 5) == 0) printf ("\n ");
> -
> - printf (" %08lX%s", info->start[i],
> - info->protect[i] ? " (RO)" : " ");
> - }
> - printf ("\n");
> - info++;
> - }
> -}
> -
> -
> -/**
> - * flash_erase: - erase flash sectors
> - */
> -
> -int flash_erase(flash_info_t *info, int s_first, int s_last)
> -{
> - int flag, prot, sect;
> - int rc = ERR_OK;
> - ulong start;
> -
> - if (info->flash_id == FLASH_UNKNOWN)
> - return ERR_UNKNOWN_FLASH_TYPE;
> -
> - if ((s_first < 0) || (s_first > s_last)) {
> - return ERR_INVAL;
> - }
> -
> - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
> - return ERR_UNKNOWN_FLASH_VENDOR;
> -
> - prot = 0;
> - for (sect=s_first; sect<=s_last; ++sect) {
> - if (info->protect[sect]) prot++;
> - }
> -
> - if (prot) return ERR_PROTECTED;
> -
> - /*
> - * Disable interrupts which might cause a timeout
> - * here. Remember that our exception vectors are
> - * at address 0 in the flash, and we don't want a
> - * (ticker) exception to happen while the flash
> - * chip is in programming mode.
> - */
> -
> - flag = disable_interrupts();
> -
> - /* Start erase on unprotected sectors */
> - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
> -
> - printf("Erasing sector %2d ... ", sect);
> -
> - /* arm simple, non interrupt dependent timer */
> - start = get_timer(0);
> -
> - if (info->protect[sect] == 0) { /* not protected */
> - u32 * volatile addr = (u32 * volatile)(info->start[sect]);
> -
> - /* erase sector: */
> - /* The strata flashs are aligned side by side on */
> - /* the data bus, so we have to write the commands */
> - /* to both chips here: */
> -
> - *addr = 0x00200020; /* erase setup */
> - *addr = 0x00D000D0; /* erase confirm */
> -
> - while ((*addr & 0x00800080) != 0x00800080) {
> - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
> - *addr = 0x00B000B0; /* suspend erase*/
> - *addr = 0x00FF00FF; /* read mode */
> - rc = ERR_TIMOUT;
> - goto outahere;
> - }
> - }
> - *addr = 0x00500050; /* clear status register cmd. */
> - *addr = 0x00FF00FF; /* reset to read mode */
> - }
> - printf("ok.\n");
> - }
> - if (ctrlc()) printf("User Interrupt!\n");
> -
> -outahere:
> - /* allow flash to settle - wait 10 ms */
> - udelay_masked(10000);
> -
> - if (flag) enable_interrupts();
> -
> - return rc;
> -}
> -
> -/**
> - * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each
> - */
> -
> -static int write_long (flash_info_t *info, ulong dest, ulong data)
> -{
> - u32 * volatile addr = (u32 * volatile)dest, val;
> - int rc = ERR_OK;
> - int flag;
> - ulong start;
> -
> - /* read array command - just for the case... */
> - *addr = 0x00FF00FF;
> -
> - /* Check if Flash is (sufficiently) erased */
> - if ((*addr & data) != data) return ERR_NOT_ERASED;
> -
> - /*
> - * Disable interrupts which might cause a timeout
> - * here. Remember that our exception vectors are
> - * at address 0 in the flash, and we don't want a
> - * (ticker) exception to happen while the flash
> - * chip is in programming mode.
> - */
> - flag = disable_interrupts();
> -
> - /* clear status register command */
> - *addr = 0x00500050;
> -
> - /* program set-up command */
> - *addr = 0x00400040;
> -
> - /* latch address/data */
> - *addr = data;
> -
> - /* arm simple, non interrupt dependent timer */
> - start = get_timer(0);
> -
> - /* wait while polling the status register */
> - while(((val = *addr) & 0x00800080) != 0x00800080) {
> - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
> - rc = ERR_TIMOUT;
> - /* suspend program command */
> - *addr = 0x00B000B0;
> - goto outahere;
> - }
> - }
> -
> - /* check for errors */
> - if(val & 0x001A001A) {
> - printf("\nFlash write error %02x at address %08lx\n",
> - (int)val, (unsigned long)dest);
> - if(val & 0x00080008) {
> - printf("Voltage range error.\n");
> - rc = ERR_PROG_ERROR;
> - goto outahere;
> - }
> - if(val & 0x00020002) {
> - printf("Device protect error.\n");
> - rc = ERR_PROTECTED;
> - goto outahere;
> - }
> - if(val & 0x00100010) {
> - printf("Programming error.\n");
> - rc = ERR_PROG_ERROR;
> - goto outahere;
> - }
> - rc = ERR_PROG_ERROR;
> - goto outahere;
> - }
> -
> -outahere:
> - /* read array command */
> - *addr = 0x00FF00FF;
> - if (flag) enable_interrupts();
> -
> - return rc;
> -}
> -
> -
> -/**
> - * write_buf: - Copy memory to flash.
> - *
> - * @param info:
> - * @param src: source of copy transaction
> - * @param addr: where to copy to
> - * @param cnt: number of bytes to copy
> - *
> - * @return error code
> - */
> -
> -/* "long" version, uses 32bit words */
> -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
> -{
> - ulong cp, wp;
> - ulong data;
> - int l;
> - int i, rc;
> -
> - wp = (addr & ~3); /* get lower word aligned address */
> -
> - /*
> - * handle unaligned start bytes
> - */
> - if ((l = addr - wp) != 0) {
> - data = 0;
> - for (i=0, cp=wp; i<l; ++i, ++cp) {
> - data = (data >> 8) | (*(uchar *)cp << 24);
> - }
> - for (; i<4 && cnt>0; ++i) {
> - data = (data >> 8) | (*src++ << 24);
> - --cnt;
> - ++cp;
> - }
> - for (; cnt==0 && i<4; ++i, ++cp) {
> - data = (data >> 8) | (*(uchar *)cp << 24);
> - }
> -
> - if ((rc = write_long(info, wp, data)) != 0) {
> - return (rc);
> - }
> - wp += 4;
> - }
> -
> - /*
> - * handle word aligned part
> - */
> - while (cnt >= 4) {
> - data = *((ulong*)src);
> - if ((rc = write_long(info, wp, data)) != 0) {
> - return (rc);
> - }
> - src += 4;
> - wp += 4;
> - cnt -= 4;
> - }
> -
> - if (cnt == 0) return ERR_OK;
> -
> - /*
> - * handle unaligned tail bytes
> - */
> - data = 0;
> - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
> - data = (data >> 8) | (*src++ << 24);
> - --cnt;
> - }
> - for (; i<4; ++i, ++cp) {
> - data = (data >> 8) | (*(uchar *)cp << 24);
> - }
> -
> - return write_long(info, wp, data);
> -}
> diff --git a/board/innokom/Makefile b/board/innokom/Makefile
> deleted file mode 100644
> index 8b58b7f..0000000
> --- a/board/innokom/Makefile
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -#
> -# (C) Copyright 2000-2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# See file CREDITS for list of people who contributed to this
> -# project.
> -#
> -# This program is free software; you can redistribute it and/or
> -# modify it under the terms of the GNU General Public License as
> -# published by the Free Software Foundation; either version 2 of
> -# the License, or (at your option) any later version.
> -#
> -# This program is distributed in the hope that it will be useful,
> -# but WITHOUT ANY WARRANTY; without even the implied warranty of
> -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> -# GNU General Public License for more details.
> -#
> -# You should have received a copy of the GNU General Public License
> -# along with this program; if not, write to the Free Software
> -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> -# MA 02111-1307 USA
> -#
> -
> -include $(TOPDIR)/config.mk
> -
> -LIB = $(obj)lib$(BOARD).o
> -
> -COBJS := innokom.o flash.o
> -
> -SRCS := $(COBJS:.o=.c)
> -OBJS := $(addprefix $(obj),$(COBJS))
> -
> -$(LIB): $(obj).depend $(OBJS)
> - $(call cmd_link_o_target, $(OBJS))
> -
> -#########################################################################
> -
> -# defines $(obj).depend target
> -include $(SRCTREE)/rules.mk
> -
> -sinclude $(obj).depend
> -
> -#########################################################################
> diff --git a/board/innokom/flash.c b/board/innokom/flash.c
> deleted file mode 100644
> index ed4b987..0000000
> --- a/board/innokom/flash.c
> +++ /dev/null
> @@ -1,421 +0,0 @@
> -/*
> - * (C) Copyright 2002
> - * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
> - *
> - * (C) Copyright 2002
> - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> - * Marius Groeger <mgroeger at sysgo.de>
> - *
> - * (C) Copyright 2002
> - * Robert Schwebel, Pengutronix, <r.schwebel at pengutronix.de>
> - *
> - * (C) Copyright 2002
> - * Auerswald GmbH & Co KG, Germany
> - * Kai-Uwe Bloem <kai-uwe.bloem at auerswald.de>
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#include <common.h>
> -#include <asm/arch/pxa-regs.h>
> -
> -/* Debugging macros ------------------------------------------------------ */
> -
> -#undef FLASH_DEBUG
> -
> -/* Some debug macros */
> -#if (FLASH_DEBUG > 2 )
> -#define PRINTK3(args...) printf(args)
> -#else
> -#define PRINTK3(args...)
> -#endif
> -
> -#if FLASH_DEBUG > 1
> -#define PRINTK2(args...) printf(args)
> -#else
> -#define PRINTK2(args...)
> -#endif
> -
> -#ifdef FLASH_DEBUG
> -#define PRINTK(args...) printf(args)
> -#else
> -#define PRINTK(args...)
> -#endif
> -
> -/* ------------------------------------------------------------------------ */
> -
> -/* Development system: we have only 16 MB Flash */
> -#ifdef CONFIG_MTD_INNOKOM_16MB
> -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB (during development) */
> -#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */
> -#endif
> -
> -/* Production system: we have 64 MB Flash */
> -#ifdef CONFIG_MTD_INNOKOM_64MB
> -#define FLASH_BANK_SIZE 0x04000000 /* 64 MB */
> -#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */
> -#endif
> -
> -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
> -
> -/**
> - * flash_init: - initialize data structures for flash chips
> - *
> - * @return: size of the flash
> - */
> -
> -ulong flash_init(void)
> -{
> - int i, j;
> - ulong size = 0;
> -
> - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
> - ulong flashbase = 0;
> - flash_info[i].flash_id =
> - (INTEL_MANUFACT & FLASH_VENDMASK) |
> - (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
> - flash_info[i].size = FLASH_BANK_SIZE;
> - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
> - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
> -
> - switch (i) {
> - case 0:
> - flashbase = PHYS_FLASH_1;
> - break;
> - default:
> - panic("configured too many flash banks!\n");
> - break;
> - }
> - for (j = 0; j < flash_info[i].sector_count; j++) {
> - flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
> - }
> - size += flash_info[i].size;
> - }
> -
> - /* Protect u-boot sectors */
> - flash_protect(FLAG_PROTECT_SET,
> - CONFIG_SYS_FLASH_BASE,
> - CONFIG_SYS_FLASH_BASE + (256*1024) - 1,
> - &flash_info[0]);
> -
> -#ifdef CONFIG_ENV_IS_IN_FLASH
> - flash_protect(FLAG_PROTECT_SET,
> - CONFIG_ENV_ADDR,
> - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
> - &flash_info[0]);
> -#endif
> -
> - return size;
> -}
> -
> -
> -/**
> - * flash_print_info: - print information about the flash situation
> - *
> - * @param info:
> - */
> -
> -void flash_print_info (flash_info_t *info)
> -{
> - int i, j;
> -
> - for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
> -
> - switch (info->flash_id & FLASH_VENDMASK) {
> -
> - case (INTEL_MANUFACT & FLASH_VENDMASK):
> - printf("Intel: ");
> - break;
> - default:
> - printf("Unknown Vendor ");
> - break;
> - }
> -
> - switch (info->flash_id & FLASH_TYPEMASK) {
> -
> - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
> - printf("28F128J3 (128Mbit)\n");
> - break;
> - default:
> - printf("Unknown Chip Type\n");
> - return;
> - }
> -
> - printf(" Size: %ld MB in %d Sectors\n",
> - info->size >> 20, info->sector_count);
> -
> - printf(" Sector Start Addresses:");
> - for (i = 0; i < info->sector_count; i++) {
> - if ((i % 5) == 0) printf ("\n ");
> -
> - printf (" %08lX%s", info->start[i],
> - info->protect[i] ? " (RO)" : " ");
> - }
> - printf ("\n");
> - info++;
> - }
> -}
> -
> -
> -/**
> - * flash_erase: - erase flash sectors
> - *
> - */
> -
> -int flash_erase(flash_info_t *info, int s_first, int s_last)
> -{
> - int flag, prot, sect;
> - int rc = ERR_OK;
> - ulong start;
> -
> - if (info->flash_id == FLASH_UNKNOWN)
> - return ERR_UNKNOWN_FLASH_TYPE;
> -
> - if ((s_first < 0) || (s_first > s_last)) {
> - return ERR_INVAL;
> - }
> -
> - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
> - return ERR_UNKNOWN_FLASH_VENDOR;
> -
> - prot = 0;
> - for (sect=s_first; sect<=s_last; ++sect) {
> - if (info->protect[sect]) prot++;
> - }
> -
> - if (prot) return ERR_PROTECTED;
> -
> - /*
> - * Disable interrupts which might cause a timeout
> - * here. Remember that our exception vectors are
> - * at address 0 in the flash, and we don't want a
> - * (ticker) exception to happen while the flash
> - * chip is in programming mode.
> - */
> -
> - flag = disable_interrupts();
> -
> - /* Start erase on unprotected sectors */
> - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
> -
> - printf("Erasing sector %2d ... ", sect);
> -
> - PRINTK("\n");
> -
> - /* arm simple, non interrupt dependent timer */
> - start = get_timer(0);
> -
> - if (info->protect[sect] == 0) { /* not protected */
> - u16 * volatile addr = (u16 * volatile)(info->start[sect]);
> -
> - PRINTK("unlocking sector\n");
> - *addr = 0x0060;
> - *addr = 0x00d0;
> - *addr = 0x00ff;
> -
> - PRINTK("erasing sector\n");
> - *addr = 0x0020;
> - PRINTK("confirming erase\n");
> - *addr = 0x00D0;
> -
> - while ((*addr & 0x0080) != 0x0080) {
> - PRINTK(".");
> - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
> - *addr = 0x00B0; /* suspend erase*/
> - *addr = 0x00FF; /* read mode */
> - rc = ERR_TIMOUT;
> - goto outahere;
> - }
> - }
> -
> - PRINTK("clearing status register\n");
> - *addr = 0x0050;
> - PRINTK("resetting to read mode");
> - *addr = 0x00FF;
> - }
> -
> - printf("ok.\n");
> - }
> -
> - if (ctrlc()) printf("User Interrupt!\n");
> -
> - outahere:
> -
> - /* allow flash to settle - wait 10 ms */
> - udelay_masked(10000);
> -
> - if (flag) enable_interrupts();
> -
> - return rc;
> -}
> -
> -
> -/**
> - * write_word: - copy memory to flash
> - *
> - * @param info:
> - * @param dest:
> - * @param data:
> - * @return:
> - */
> -
> -static int write_word (flash_info_t *info, ulong dest, ushort data)
> -{
> - volatile u16 *addr = (u16 *)dest, val;
> - int rc = ERR_OK;
> - int flag;
> - ulong start;
> -
> - /* Check if Flash is (sufficiently) erased */
> - if ((*addr & data) != data) return ERR_NOT_ERASED;
> -
> - /*
> - * Disable interrupts which might cause a timeout
> - * here. Remember that our exception vectors are
> - * at address 0 in the flash, and we don't want a
> - * (ticker) exception to happen while the flash
> - * chip is in programming mode.
> - */
> - flag = disable_interrupts();
> -
> - /* clear status register command */
> - *addr = 0x50;
> -
> - /* program set-up command */
> - *addr = 0x40;
> -
> - /* latch address/data */
> - *addr = data;
> -
> - /* arm simple, non interrupt dependent timer */
> - start = get_timer(0);
> -
> - /* wait while polling the status register */
> - while(((val = *addr) & 0x80) != 0x80) {
> - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
> - rc = ERR_TIMOUT;
> - *addr = 0xB0; /* suspend program command */
> - goto outahere;
> - }
> - }
> -
> - if(val & 0x1A) { /* check for error */
> - printf("\nFlash write error %02x at address %08lx\n",
> - (int)val, (unsigned long)dest);
> - if(val & (1<<3)) {
> - printf("Voltage range error.\n");
> - rc = ERR_PROG_ERROR;
> - goto outahere;
> - }
> - if(val & (1<<1)) {
> - printf("Device protect error.\n");
> - rc = ERR_PROTECTED;
> - goto outahere;
> - }
> - if(val & (1<<4)) {
> - printf("Programming error.\n");
> - rc = ERR_PROG_ERROR;
> - goto outahere;
> - }
> - rc = ERR_PROG_ERROR;
> - goto outahere;
> - }
> -
> - outahere:
> -
> - *addr = 0xFF; /* read array command */
> - if (flag) enable_interrupts();
> -
> - return rc;
> -}
> -
> -
> -/**
> - * write_buf: - Copy memory to flash.
> - *
> - * @param info:
> - * @param src: source of copy transaction
> - * @param addr: where to copy to
> - * @param cnt: number of bytes to copy
> - *
> - * @return error code
> - */
> -
> -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
> -{
> - ulong cp, wp;
> - ushort data;
> - int l;
> - int i, rc;
> -
> - wp = (addr & ~1); /* get lower word aligned address */
> -
> - /*
> - * handle unaligned start bytes
> - */
> - if ((l = addr - wp) != 0) {
> - data = 0;
> - for (i=0, cp=wp; i<l; ++i, ++cp) {
> - data = (data >> 8) | (*(uchar *)cp << 8);
> - }
> - for (; i<2 && cnt>0; ++i) {
> - data = (data >> 8) | (*src++ << 8);
> - --cnt;
> - ++cp;
> - }
> - for (; cnt==0 && i<2; ++i, ++cp) {
> - data = (data >> 8) | (*(uchar *)cp << 8);
> - }
> -
> - if ((rc = write_word(info, wp, data)) != 0) {
> - return (rc);
> - }
> - wp += 2;
> - }
> -
> - /*
> - * handle word aligned part
> - */
> - while (cnt >= 2) {
> - /* data = *((vushort*)src); */
> - data = *((ushort*)src);
> - if ((rc = write_word(info, wp, data)) != 0) {
> - return (rc);
> - }
> - src += 2;
> - wp += 2;
> - cnt -= 2;
> - }
> -
> - if (cnt == 0) return ERR_OK;
> -
> - /*
> - * handle unaligned tail bytes
> - */
> - data = 0;
> - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
> - data = (data >> 8) | (*src++ << 8);
> - --cnt;
> - }
> - for (; i<2; ++i, ++cp) {
> - data = (data >> 8) | (*(uchar *)cp << 8);
> - }
> -
> - return write_word(info, wp, data);
> -}
> diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
> deleted file mode 100644
> index 22de7e3..0000000
> --- a/board/innokom/innokom.c
> +++ /dev/null
> @@ -1,190 +0,0 @@
> -/*
> - * (C) Copyright 2002
> - * Robert Schwebel, Pengutronix, r.schwebel at pengutronix.de
> - * Kyle Harris, Nexus Technologies, Inc., kharris at nexus-tech.net
> - * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger at sysgo.de
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#include <common.h>
> -#include <netdev.h>
> -#include <asm/arch/pxa-regs.h>
> -#include <asm/mach-types.h>
> -#include <asm/io.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#ifdef CONFIG_SHOW_BOOT_PROGRESS
> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
> -#else
> -# define SHOW_BOOT_PROGRESS(arg)
> -#endif
> -
> -/**
> - * i2c_init_board - reset i2c bus. When the board is powercycled during a
> - * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
> - * The Innokom board has GPIO70 connected to SCLK which can be toggled
> - * until all chips think that their current cycles are finished.
> - */
> -int i2c_init_board(void)
> -{
> - int i;
> -
> - /* set gpio pin low _before_ we change direction to output */
> - writel(GPIO_bit(70), GPCR(70));
> -
> - /* now toggle between output=low and high-impedance */
> - for (i = 0; i < 20; i++) {
> - writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */
> - udelay(10);
> - writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */
> - udelay(10);
> - }
> -
> - return 0;
> -}
> -
> -
> -/**
> - * misc_init_r: - misc initialisation routines
> - */
> -
> -int misc_init_r(void)
> -{
> - char *str;
> -
> - /* determine if the software update key is pressed during startup */
> - if (readl(GPLR0) & 0x00000800) {
> - printf("using bootcmd_normal (sw-update button not pressed)\n");
> - str = getenv("bootcmd_normal");
> - } else {
> - printf("using bootcmd_update (sw-update button pressed)\n");
> - str = getenv("bootcmd_update");
> - }
> -
> - setenv("bootcmd",str);
> -
> - return 0;
> -}
> -
> -
> -/**
> - * board_init: - setup some data structures
> - *
> - * @return: 0 in case of success
> - */
> -
> -int board_init (void)
> -{
> - /* We have RAM, disable cache */
> - dcache_disable();
> - icache_disable();
> -
> - gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;
> - gd->bd->bi_boot_params = 0xa0000100;
> - gd->bd->bi_baudrate = CONFIG_BAUDRATE;
> -
> - return 0;
> -}
> -
> -extern void pxa_dram_init(void);
> -int dram_init(void)
> -{
> - pxa_dram_init();
> - gd->ram_size = PHYS_SDRAM_1_SIZE;
> - return 0;
> -}
> -
> -void dram_init_banksize(void)
> -{
> - gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> -}
> -
> -/**
> - * innokom_set_led: - switch LEDs on or off
> - *
> - * @param led: LED to switch (0,1,2)
> - * @param state: switch on (1) or off (0)
> - */
> -
> -void innokom_set_led(int led, int state)
> -{
> - switch(led) {
> -/*
> - case 0: if (state==1) {
> - GPCR0 |= CSB226_USER_LED0;
> - } else if (state==0) {
> - GPSR0 |= CSB226_USER_LED0;
> - }
> - break;
> -
> - case 1: if (state==1) {
> - GPCR0 |= CSB226_USER_LED1;
> - } else if (state==0) {
> - GPSR0 |= CSB226_USER_LED1;
> - }
> - break;
> -
> - case 2: if (state==1) {
> - GPCR0 |= CSB226_USER_LED2;
> - } else if (state==0) {
> - GPSR0 |= CSB226_USER_LED2;
> - }
> - break;
> -*/
> - }
> -
> - return;
> -}
> -
> -
> -/**
> - * show_boot_progress: - indicate state of the boot process
> - *
> - * @param status: Status number - see README for details.
> - *
> - * The CSB226 does only have 3 LEDs, so we switch them on at the most
> - * important states (1, 5, 15).
> - */
> -
> -void show_boot_progress (int status)
> -{
> - switch(status) {
> -/*
> - case 1: csb226_set_led(0,1); break;
> - case 5: csb226_set_led(1,1); break;
> - case 15: csb226_set_led(2,1); break;
> -*/
> - }
> -
> - return;
> -}
> -
> -#ifdef CONFIG_CMD_NET
> -int board_eth_init(bd_t *bis)
> -{
> - int rc = 0;
> -#ifdef CONFIG_SMC91111
> - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
> -#endif
> - return rc;
> -}
> -#endif
> diff --git a/boards.cfg b/boards.cfg
> index 8bd91c5..a523c95 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -209,8 +209,6 @@ balloon3 arm pxa
> cerf250 arm pxa
> colibri_pxa270 arm pxa
> cradle arm pxa
> -csb226 arm pxa
> -innokom arm pxa
> lubbock arm pxa
> palmld arm pxa
> palmtc arm pxa
> diff --git a/include/configs/csb226.h b/include/configs/csb226.h
> deleted file mode 100644
> index 804469b..0000000
> --- a/include/configs/csb226.h
> +++ /dev/null
> @@ -1,506 +0,0 @@
> -/*
> - * (C) Copyright 2000, 2001, 2002
> - * Robert Schwebel, Pengutronix, r.schwebel at pengutronix.de.
> - *
> - * Configuration for the Cogent CSB226 board. For details see
> - * http://www.cogcomp.com/csb_csb226.htm
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -/*
> - * include/configs/csb226.h - configuration options, board specific
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -#define DEBUG 1
> -
> -/*
> - * High Level Configuration Options
> - * (easy to change)
> - */
> -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
> -#define CONFIG_CSB226 1 /* on a CSB226 board */
> -
> -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
> - /* for timer/console/ethernet */
> -
> -/* we will never enable dcache, because we have to setup MMU first */
> -#define CONFIG_SYS_DCACHE_OFF
> -#define CONFIG_SYS_TEXT_BASE 0x0
> -/*
> - * Hardware drivers
> - */
> -
> -/*
> - * select serial console configuration
> - */
> -#define CONFIG_PXA_SERIAL
> -#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
> -
> -/* allow to overwrite serial and ethaddr */
> -#define CONFIG_ENV_OVERWRITE
> -
> -#define CONFIG_BAUDRATE 19200
> -#undef CONFIG_MISC_INIT_R /* not used yet */
> -
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#define CONFIG_BOOTP_BOOTPATH
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_HOSTNAME
> -
> -
> -/*
> - * Command line configuration.
> - */
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_BDI
> -#define CONFIG_CMD_LOADB
> -#define CONFIG_CMD_IMI
> -#define CONFIG_CMD_FLASH
> -#define CONFIG_CMD_MEMORY
> -#define CONFIG_CMD_NET
> -#define CONFIG_CMD_SAVEENV
> -#define CONFIG_CMD_RUN
> -#define CONFIG_CMD_ASKENV
> -#define CONFIG_CMD_ECHO
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_CACHE
> -
> -
> -#define CONFIG_BOOTDELAY 3
> -#define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
> -#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
> -#define CONFIG_NETMASK 255.255.255.0
> -#define CONFIG_IPADDR 192.168.1.56
> -#define CONFIG_SERVERIP 192.168.1.5
> -#define CONFIG_BOOTCOMMAND "bootm 0x40000"
> -#define CONFIG_SHOW_BOOT_PROGRESS
> -
> -#define CONFIG_CMDLINE_TAG 1
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
> -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
> -#endif
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -
> -/*
> - * Size of malloc() pool; this lives below the uppermost 128 KiB which are
> - * used for the RAM copy of the uboot code
> - *
> - */
> -#define CONFIG_SYS_MALLOC_LEN (128*1024)
> -
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
> -#define CONFIG_SYS_CBSIZE 128 /* Console I/O Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
> -
> -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
> -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
> -
> -#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
> - /* RS: where is this documented? */
> - /* RS: is this where U-Boot is */
> - /* RS: relocated to in RAM? */
> -
> -#define CONFIG_SYS_HZ 1000
> - /* RS: the oscillator is actually 3680130?? */
> -#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
> - /* 0101000001 */
> - /* ^^^^^ Memory Speed 99.53 MHz */
> - /* ^^ Run Mode Speed = 2x Mem Speed */
> - /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
> -
> -#define CONFIG_SYS_MONITOR_LEN 0x1c000 /* 112 KiB */
> -
> - /* valid baudrates */
> -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> -
> -/*
> - * Network chip
> - */
> -#define CONFIG_CS8900
> -#define CONFIG_CS8900_BUS32
> -#define CONFIG_CS8900_BASE 0x08000000
> -
> -/*
> - * Stack sizes
> - *
> - * The stack sizes are set up in start.S using the settings below
> - */
> -#define CONFIG_STACKSIZE (128*1024) /* regular stack */
> -#ifdef CONFIG_USE_IRQ
> -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
> -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
> -#endif
> -
> -/*
> - * Physical Memory Map
> - */
> -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
> -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
> -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
> -
> -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
> -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
> -
> -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */
> -#define CONFIG_SYS_DRAM_SIZE 0x02000000
> -
> -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
> -
> -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
> -
> -# if 0
> -/* FIXME: switch to _documented_ registers */
> -/*
> - * GPIO settings
> - *
> - * GP15 == nCS1 is 1
> - * GP24 == SFRM is 1
> - * GP25 == TXD is 1
> - * GP33 == nCS5 is 1
> - * GP39 == FFTXD is 1
> - * GP41 == RTS is 1
> - * GP47 == TXD is 1
> - * GP49 == nPWE is 1
> - * GP62 == LED_B is 1
> - * GP63 == TDM_OE is 1
> - * GP78 == nCS2 is 1
> - * GP79 == nCS3 is 1
> - * GP80 == nCS4 is 1
> - */
> -#define CONFIG_SYS_GPSR0_VAL 0x03008000
> -#define CONFIG_SYS_GPSR1_VAL 0xC0028282
> -#define CONFIG_SYS_GPSR2_VAL 0x0001C000
> -
> -/* GP02 == DON_RST is 0
> - * GP23 == SCLK is 0
> - * GP45 == USB_ACT is 0
> - * GP60 == PLLEN is 0
> - * GP61 == LED_A is 0
> - * GP73 == SWUPD_LED is 0
> - */
> -#define CONFIG_SYS_GPCR0_VAL 0x00800004
> -#define CONFIG_SYS_GPCR1_VAL 0x30002000
> -#define CONFIG_SYS_GPCR2_VAL 0x00000100
> -
> -/* GP00 == DON_READY is input
> - * GP01 == DON_OK is input
> - * GP02 == DON_RST is output
> - * GP03 == RESET_IND is input
> - * GP07 == RES11 is input
> - * GP09 == RES12 is input
> - * GP11 == SWUPDATE is input
> - * GP14 == nPOWEROK is input
> - * GP15 == nCS1 is output
> - * GP17 == RES22 is input
> - * GP18 == RDY is input
> - * GP23 == SCLK is output
> - * GP24 == SFRM is output
> - * GP25 == TXD is output
> - * GP26 == RXD is input
> - * GP32 == RES21 is input
> - * GP33 == nCS5 is output
> - * GP34 == FFRXD is input
> - * GP35 == CTS is input
> - * GP39 == FFTXD is output
> - * GP41 == RTS is output
> - * GP42 == USB_OK is input
> - * GP45 == USB_ACT is output
> - * GP46 == RXD is input
> - * GP47 == TXD is output
> - * GP49 == nPWE is output
> - * GP58 == nCPUBUSINT is input
> - * GP59 == LANINT is input
> - * GP60 == PLLEN is output
> - * GP61 == LED_A is output
> - * GP62 == LED_B is output
> - * GP63 == TDM_OE is output
> - * GP64 == nDSPINT is input
> - * GP65 == STRAP0 is input
> - * GP67 == STRAP1 is input
> - * GP69 == STRAP2 is input
> - * GP70 == STRAP3 is input
> - * GP71 == STRAP4 is input
> - * GP73 == SWUPD_LED is output
> - * GP78 == nCS2 is output
> - * GP79 == nCS3 is output
> - * GP80 == nCS4 is output
> - */
> -#define CONFIG_SYS_GPDR0_VAL 0x03808004
> -#define CONFIG_SYS_GPDR1_VAL 0xF002A282
> -#define CONFIG_SYS_GPDR2_VAL 0x0001C200
> -
> -/* GP15 == nCS1 is AF10
> - * GP18 == RDY is AF01
> - * GP23 == SCLK is AF10
> - * GP24 == SFRM is AF10
> - * GP25 == TXD is AF10
> - * GP26 == RXD is AF01
> - * GP33 == nCS5 is AF10
> - * GP34 == FFRXD is AF01
> - * GP35 == CTS is AF01
> - * GP39 == FFTXD is AF10
> - * GP41 == RTS is AF10
> - * GP46 == RXD is AF10
> - * GP47 == TXD is AF01
> - * GP49 == nPWE is AF10
> - * GP78 == nCS2 is AF10
> - * GP79 == nCS3 is AF10
> - * GP80 == nCS4 is AF10
> - */
> -#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
> -#define CONFIG_SYS_GAFR0_U_VAL 0x001A8010
> -#define CONFIG_SYS_GAFR1_L_VAL 0x60088058
> -#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
> -#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
> -#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
> -
> -
> -/* FIXME: set GPIO_RER/FER */
> -
> -/* RDH = 1
> - * PH = 1
> - * VFS = 1
> - * BFS = 1
> - * SSS = 1
> - */
> -#define CONFIG_SYS_PSSR_VAL 0x37
> -
> -/*
> - * Memory settings
> - *
> - * This is the configuration for nCS0/1 -> flash banks
> - * configuration for nCS1:
> - * [31] 0 - Slower Device
> - * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
> - * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
> - * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
> - * [19] 1 - 16 Bit bus width
> - * [18:16] 000 - nonburst RAM or FLASH
> - * configuration for nCS0:
> - * [15] 0 - Slower Device
> - * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
> - * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
> - * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
> - * [03] 1 - 16 Bit bus width
> - * [02:00] 000 - nonburst RAM or FLASH
> - */
> -#define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */
> -
> -/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
> - * configuration for nCS3: DSP
> - * [31] 0 - Slower Device
> - * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
> - * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
> - * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
> - * [19] 1 - 16 Bit bus width
> - * [18:16] 100 - variable latency I/O
> - * configuration for nCS2: TDM-Switch
> - * [15] 0 - Slower Device
> - * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
> - * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
> - * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
> - * [03] 1 - 16 Bit bus width
> - * [02:00] 100 - variable latency I/O
> - */
> -#define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */
> -
> -/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
> - *
> - * configuration for nCS5: LAN Controller
> - * [31] 0 - Slower Device
> - * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
> - * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
> - * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
> - * [19] 1 - 16 Bit bus width
> - * [18:16] 100 - variable latency I/O
> - * configuration for nCS4: ExtBus
> - * [15] 0 - Slower Device
> - * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
> - * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
> - * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
> - * [03] 1 - 16 Bit bus width
> - * [02:00] 100 - variable latency I/O
> - */
> -#define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
> -
> -/* MDCNFG: SDRAM Configuration Register
> - *
> - * [31:29] 000 - reserved
> - * [28] 0 - no SA1111 compatiblity mode
> - * [27] 0 - latch return data with return clock
> - * [26] 0 - alternate addressing for pair 2/3
> - * [25:24] 00 - timings
> - * [23] 0 - internal banks in lower partition 2/3 (not used)
> - * [22:21] 00 - row address bits for partition 2/3 (not used)
> - * [20:19] 00 - column address bits for partition 2/3 (not used)
> - * [18] 0 - SDRAM partition 2/3 width is 32 bit
> - * [17] 0 - SDRAM partition 3 disabled
> - * [16] 0 - SDRAM partition 2 disabled
> - * [15:13] 000 - reserved
> - * [12] 1 - SA1111 compatiblity mode
> - * [11] 1 - latch return data with return clock
> - * [10] 0 - no alternate addressing for pair 0/1
> - * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
> - * [7] 1 - 4 internal banks in lower partition pair
> - * [06:05] 10 - 13 row address bits for partition 0/1
> - * [04:03] 01 - 9 column address bits for partition 0/1
> - * [02] 0 - SDRAM partition 0/1 width is 32 bit
> - * [01] 0 - disable SDRAM partition 1
> - * [00] 1 - enable SDRAM partition 0
> - */
> -/* use the configuration above but disable partition 0 */
> -#define CONFIG_SYS_MDCNFG_VAL 0x000019c8
> -
> -/* MDREFR: SDRAM Refresh Control Register
> - *
> - * [32:26] 0 - reserved
> - * [25] 0 - K2FREE: not free running
> - * [24] 0 - K1FREE: not free running
> - * [23] 1 - K0FREE: not free running
> - * [22] 0 - SLFRSH: self refresh disabled
> - * [21] 0 - reserved
> - * [20] 0 - APD: no auto power down
> - * [19] 0 - K2DB2: SDCLK2 is MemClk
> - * [18] 0 - K2RUN: disable SDCLK2
> - * [17] 0 - K1DB2: SDCLK1 is MemClk
> - * [16] 1 - K1RUN: enable SDCLK1
> - * [15] 1 - E1PIN: SDRAM clock enable
> - * [14] 1 - K0DB2: SDCLK0 is MemClk
> - * [13] 0 - K0RUN: disable SDCLK0
> - * [12] 1 - E0PIN: disable SDCKE0
> - * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
> - */
> -#define CONFIG_SYS_MDREFR_VAL 0x0081D018
> -
> -/* MDMRS: Mode Register Set Configuration Register
> - *
> - * [31] 0 - reserved
> - * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
> - * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
> - * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
> - * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
> - * [15] 0 - reserved
> - * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
> - * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
> - * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
> - * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
> - */
> -#define CONFIG_SYS_MDMRS_VAL 0x00020022
> -
> -/*
> - * PCMCIA and CF Interfaces
> - */
> -#define CONFIG_SYS_MECR_VAL 0x00000000
> -#define CONFIG_SYS_MCMEM0_VAL 0x00000000
> -#define CONFIG_SYS_MCMEM1_VAL 0x00000000
> -#define CONFIG_SYS_MCATT0_VAL 0x00000000
> -#define CONFIG_SYS_MCATT1_VAL 0x00000000
> -#define CONFIG_SYS_MCIO0_VAL 0x00000000
> -#define CONFIG_SYS_MCIO1_VAL 0x00000000
> -#endif
> -
> -/*
> - * GPIO settings
> - */
> -#define CONFIG_SYS_GPSR0_VAL 0xFFFFFFFF
> -#define CONFIG_SYS_GPSR1_VAL 0xFFFFFFFF
> -#define CONFIG_SYS_GPSR2_VAL 0xFFFFFFFF
> -#define CONFIG_SYS_GPCR0_VAL 0x08022080
> -#define CONFIG_SYS_GPCR1_VAL 0x00000000
> -#define CONFIG_SYS_GPCR2_VAL 0x00000000
> -#define CONFIG_SYS_GPDR0_VAL 0xCD82A878
> -#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB80
> -#define CONFIG_SYS_GPDR2_VAL 0x0001FFFF
> -#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
> -#define CONFIG_SYS_GAFR0_U_VAL 0xA5254010
> -#define CONFIG_SYS_GAFR1_L_VAL 0x599A9550
> -#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA
> -#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
> -#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
> -
> -/* FIXME: set GPIO_RER/FER */
> -
> -#define CONFIG_SYS_PSSR_VAL 0x20
> -
> -#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
> -#define CONFIG_SYS_CKEN 0x0
> -
> -/*
> - * Memory settings
> - */
> -
> -#define CONFIG_SYS_MSC0_VAL 0x2ef15af0
> -#define CONFIG_SYS_MSC1_VAL 0x00003ff4
> -#define CONFIG_SYS_MSC2_VAL 0x7ff07ff0
> -#define CONFIG_SYS_MDCNFG_VAL 0x09a909a9
> -#define CONFIG_SYS_MDREFR_VAL 0x038ff030
> -#define CONFIG_SYS_MDMRS_VAL 0x00220022
> -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
> -#define CONFIG_SYS_SXCNFG_VAL 0x00000000
> -
> -/*
> - * PCMCIA and CF Interfaces
> - */
> -#define CONFIG_SYS_MECR_VAL 0x00000000
> -#define CONFIG_SYS_MCMEM0_VAL 0x00000000
> -#define CONFIG_SYS_MCMEM1_VAL 0x00000000
> -#define CONFIG_SYS_MCATT0_VAL 0x00000000
> -#define CONFIG_SYS_MCATT1_VAL 0x00000000
> -#define CONFIG_SYS_MCIO0_VAL 0x00000000
> -#define CONFIG_SYS_MCIO1_VAL 0x00000000
> -
> -#define CSB226_USER_LED0 0x00000008
> -#define CSB226_USER_LED1 0x00000010
> -#define CSB226_USER_LED2 0x00000020
> -
> -
> -/*
> - * FLASH and environment organization
> - */
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
> -
> -/* timeout values are in ticks */
> -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
> -
> -#define CONFIG_ENV_IS_IN_FLASH 1
> -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
> - /* Addr of Environment Sector */
> -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
> -
> -#endif /* __CONFIG_H */
> diff --git a/include/configs/innokom.h b/include/configs/innokom.h
> deleted file mode 100644
> index a0a3da1..0000000
> --- a/include/configs/innokom.h
> +++ /dev/null
> @@ -1,507 +0,0 @@
> -/*
> - * (C) Copyright 2000, 2001, 2002
> - * Robert Schwebel, Pengutronix, r.schwebel at pengutronix.de.
> - *
> - * Configuration for the Auerswald Innokom CPU board.
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -/*
> - * include/configs/innokom.h - configuration options, board specific
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - * (easy to change)
> - */
> -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
> -#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
> -
> -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
> - /* for timer/console/ethernet */
> -
> -#define CONFIG_SYS_TEXT_BASE 0x0
> -
> -/* we will never enable dcache, because we have to setup MMU first */
> -#define CONFIG_SYS_DCACHE_OFF
> -
> -/*
> - * Hardware drivers
> - */
> -
> -/*
> - * select serial console configuration
> - */
> -#define CONFIG_PXA_SERIAL
> -#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
> -
> -/* allow to overwrite serial and ethaddr */
> -#define CONFIG_ENV_OVERWRITE
> -
> -#define CONFIG_BAUDRATE 19200
> -#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
> -
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#define CONFIG_BOOTP_BOOTPATH
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_HOSTNAME
> -
> -
> -/*
> - * Command line configuration.
> - */
> -
> -#define CONFIG_CMD_ASKENV
> -#define CONFIG_CMD_BDI
> -#define CONFIG_CMD_CACHE
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_ECHO
> -#define CONFIG_CMD_SAVEENV
> -#define CONFIG_CMD_FLASH
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_IMI
> -#define CONFIG_CMD_LOADB
> -#define CONFIG_CMD_MEMORY
> -#define CONFIG_CMD_NET
> -#define CONFIG_CMD_RUN
> -
> -
> -#define CONFIG_BOOTDELAY 3
> -/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
> -#define CONFIG_BOOTARGS "console=ttyS0,19200"
> -#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
> -#define CONFIG_NETMASK 255.255.255.0
> -#define CONFIG_IPADDR 192.168.1.56
> -#define CONFIG_SERVERIP 192.168.1.2
> -#define CONFIG_BOOTCOMMAND "bootm 0x40000"
> -#define CONFIG_SHOW_BOOT_PROGRESS
> -
> -#define CONFIG_CMDLINE_TAG 1
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -
> -/*
> - * Size of malloc() pool
> - */
> -#define CONFIG_SYS_MALLOC_LEN (256*1024)
> -
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
> -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
> -
> -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
> -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
> -
> -#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */
> -
> -#define CONFIG_SYS_HZ 1000
> - /* RS: the oscillator is actually 3680130?? */
> -
> -#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
> - /* 0101000001 */
> - /* ^^^^^ Memory Speed 99.53 MHz */
> - /* ^^ Run Mode Speed = 2x Mem Speed */
> - /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
> -
> -#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
> -
> - /* valid baudrates */
> -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> -
> -/*
> - * I2C bus
> - */
> -#define CONFIG_I2C_MV 1
> -#define CONFIG_MV_I2C_REG 0x40301680
> -#define CONFIG_HARD_I2C 1
> -#define CONFIG_SYS_I2C_SPEED 50000
> -#define CONFIG_SYS_I2C_SLAVE 0xfe
> -
> -#define CONFIG_ENV_IS_IN_EEPROM 1
> -
> -#define CONFIG_ENV_OFFSET 0x00 /* environment starts here */
> -#define CONFIG_ENV_SIZE 1024 /* 1 KiB */
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
> -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of address */
> -#define CONFIG_SYS_EEPROM_SIZE 4096 /* size in bytes */
> -#define CONFIG_SYS_I2C_INIT_BOARD 1 /* board has it's own init */
> -
> -/*
> - * SMSC91C111 Network Card
> - */
> -#define CONFIG_SMC91111 1
> -#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
> -#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
> -#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
> -#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */
> -#undef CONFIG_SHOW_ACTIVITY
> -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
> -
> -/*
> - * Stack sizes
> - *
> - * The stack sizes are set up in start.S using the settings below
> - */
> -#define CONFIG_STACKSIZE (128*1024) /* regular stack */
> -#ifdef CONFIG_USE_IRQ
> -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
> -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
> -#endif
> -
> -/*
> - * Physical Memory Map
> - */
> -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
> -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
> -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
> -
> -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
> -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
> -
> -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */
> -#define CONFIG_SYS_DRAM_SIZE 0x04000000
> -
> -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
> -
> -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
> -
> -/*
> - * JFFS2 partitions
> - *
> - */
> -/* development flash */
> -#define CONFIG_MTD_INNOKOM_16MB 1
> -#undef CONFIG_MTD_INNOKOM_64MB
> -
> -/* production flash */
> -/*
> -#define CONFIG_MTD_INNOKOM_64MB 1
> -#undef CONFIG_MTD_INNOKOM_16MB
> -*/
> -
> -/* No command line, one static partition, whole device */
> -#undef CONFIG_CMD_MTDPARTS
> -#define CONFIG_JFFS2_DEV "nor0"
> -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
> -#define CONFIG_JFFS2_PART_OFFSET 0x00000000
> -
> -/* mtdparts command line support */
> -/* Note: fake mtd_id used, no linux mtd map file */
> -/*
> -#define CONFIG_CMD_MTDPARTS
> -#define MTDIDS_DEFAULT "nor0=innokom-0"
> -*/
> -
> -/* development flash */
> -/*
> -#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
> -*/
> -
> -/* production flash */
> -/*
> -#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
> -*/
> -
> -/*
> - * GPIO settings
> - *
> - * GP15 == nCS1 is 1
> - * GP24 == SFRM is 1
> - * GP25 == TXD is 1
> - * GP33 == nCS5 is 1
> - * GP39 == FFTXD is 1
> - * GP41 == RTS is 1
> - * GP47 == TXD is 1
> - * GP49 == nPWE is 1
> - * GP62 == LED_B is 1
> - * GP63 == TDM_OE is 1
> - * GP78 == nCS2 is 1
> - * GP79 == nCS3 is 1
> - * GP80 == nCS4 is 1
> - */
> -#define CONFIG_SYS_GPSR0_VAL 0x03008000
> -#define CONFIG_SYS_GPSR1_VAL 0xC0028282
> -#define CONFIG_SYS_GPSR2_VAL 0x0001C000
> -
> -/* GP02 == DON_RST is 0
> - * GP23 == SCLK is 0
> - * GP45 == USB_ACT is 0
> - * GP60 == PLLEN is 0
> - * GP61 == LED_A is 0
> - * GP73 == SWUPD_LED is 0
> - */
> -#define CONFIG_SYS_GPCR0_VAL 0x00800004
> -#define CONFIG_SYS_GPCR1_VAL 0x30002000
> -#define CONFIG_SYS_GPCR2_VAL 0x00000100
> -
> -/* GP00 == DON_READY is input
> - * GP01 == DON_OK is input
> - * GP02 == DON_RST is output
> - * GP03 == RESET_IND is input
> - * GP07 == RES11 is input
> - * GP09 == RES12 is input
> - * GP11 == SWUPDATE is input
> - * GP14 == nPOWEROK is input
> - * GP15 == nCS1 is output
> - * GP17 == RES22 is input
> - * GP18 == RDY is input
> - * GP23 == SCLK is output
> - * GP24 == SFRM is output
> - * GP25 == TXD is output
> - * GP26 == RXD is input
> - * GP32 == RES21 is input
> - * GP33 == nCS5 is output
> - * GP34 == FFRXD is input
> - * GP35 == CTS is input
> - * GP39 == FFTXD is output
> - * GP41 == RTS is output
> - * GP42 == USB_OK is input
> - * GP45 == USB_ACT is output
> - * GP46 == RXD is input
> - * GP47 == TXD is output
> - * GP49 == nPWE is output
> - * GP58 == nCPUBUSINT is input
> - * GP59 == LANINT is input
> - * GP60 == PLLEN is output
> - * GP61 == LED_A is output
> - * GP62 == LED_B is output
> - * GP63 == TDM_OE is output
> - * GP64 == nDSPINT is input
> - * GP65 == STRAP0 is input
> - * GP67 == STRAP1 is input
> - * GP69 == STRAP2 is input
> - * GP70 == STRAP3 is input
> - * GP71 == STRAP4 is input
> - * GP73 == SWUPD_LED is output
> - * GP78 == nCS2 is output
> - * GP79 == nCS3 is output
> - * GP80 == nCS4 is output
> - */
> -#define CONFIG_SYS_GPDR0_VAL 0x03808004
> -#define CONFIG_SYS_GPDR1_VAL 0xF002A282
> -#define CONFIG_SYS_GPDR2_VAL 0x0001C200
> -
> -/* GP15 == nCS1 is AF10
> - * GP18 == RDY is AF01
> - * GP23 == SCLK is AF10
> - * GP24 == SFRM is AF10
> - * GP25 == TXD is AF10
> - * GP26 == RXD is AF01
> - * GP33 == nCS5 is AF10
> - * GP34 == FFRXD is AF01
> - * GP35 == CTS is AF01
> - * GP39 == FFTXD is AF10
> - * GP41 == RTS is AF10
> - * GP46 == RXD is AF10
> - * GP47 == TXD is AF01
> - * GP49 == nPWE is AF10
> - * GP78 == nCS2 is AF10
> - * GP79 == nCS3 is AF10
> - * GP80 == nCS4 is AF10
> - */
> -#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
> -#define CONFIG_SYS_GAFR0_U_VAL 0x001A8010
> -#define CONFIG_SYS_GAFR1_L_VAL 0x60088058
> -#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
> -#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
> -#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
> -
> -
> -/* FIXME: set GPIO_RER/FER */
> -
> -/* RDH = 1
> - * PH = 1
> - * VFS = 1
> - * BFS = 1
> - * SSS = 1
> - */
> -#define CONFIG_SYS_PSSR_VAL 0x37
> -
> -#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
> -#define CONFIG_SYS_CKEN 0x0
> -
> -/*
> - * Memory settings
> - *
> - * This is the configuration for nCS0/1 -> flash banks
> - * configuration for nCS1:
> - * [31] 0 - Slower Device
> - * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
> - * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
> - * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
> - * [19] 1 - 16 Bit bus width
> - * [18:16] 000 - nonburst RAM or FLASH
> - * configuration for nCS0:
> - * [15] 0 - Slower Device
> - * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
> - * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
> - * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
> - * [03] 1 - 16 Bit bus width
> - * [02:00] 000 - nonburst RAM or FLASH
> - */
> -#define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */
> -
> -/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
> - * configuration for nCS3: DSP
> - * [31] 0 - Slower Device
> - * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
> - * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
> - * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
> - * [19] 1 - 16 Bit bus width
> - * [18:16] 100 - variable latency I/O
> - * configuration for nCS2: TDM-Switch
> - * [15] 0 - Slower Device
> - * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
> - * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
> - * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
> - * [03] 1 - 16 Bit bus width
> - * [02:00] 100 - variable latency I/O
> - */
> -#define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */
> -
> -/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
> - *
> - * configuration for nCS5: LAN Controller
> - * [31] 0 - Slower Device
> - * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
> - * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
> - * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
> - * [19] 1 - 16 Bit bus width
> - * [18:16] 100 - variable latency I/O
> - * configuration for nCS4: ExtBus
> - * [15] 0 - Slower Device
> - * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
> - * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
> - * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
> - * [03] 1 - 16 Bit bus width
> - * [02:00] 100 - variable latency I/O
> - */
> -#define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
> -
> -/* MDCNFG: SDRAM Configuration Register
> - *
> - * [31:29] 000 - reserved
> - * [28] 0 - no SA1111 compatiblity mode
> - * [27] 0 - latch return data with return clock
> - * [26] 0 - alternate addressing for pair 2/3
> - * [25:24] 00 - timings
> - * [23] 0 - internal banks in lower partition 2/3 (not used)
> - * [22:21] 00 - row address bits for partition 2/3 (not used)
> - * [20:19] 00 - column address bits for partition 2/3 (not used)
> - * [18] 0 - SDRAM partition 2/3 width is 32 bit
> - * [17] 0 - SDRAM partition 3 disabled
> - * [16] 0 - SDRAM partition 2 disabled
> - * [15:13] 000 - reserved
> - * [12] 1 - SA1111 compatiblity mode
> - * [11] 1 - latch return data with return clock
> - * [10] 0 - no alternate addressing for pair 0/1
> - * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
> - * [7] 1 - 4 internal banks in lower partition pair
> - * [06:05] 10 - 13 row address bits for partition 0/1
> - * [04:03] 01 - 9 column address bits for partition 0/1
> - * [02] 0 - SDRAM partition 0/1 width is 32 bit
> - * [01] 0 - disable SDRAM partition 1
> - * [00] 1 - enable SDRAM partition 0
> - */
> -/* use the configuration above but disable partition 0 */
> -#define CONFIG_SYS_MDCNFG_VAL 0x000019c8
> -
> -/* MDREFR: SDRAM Refresh Control Register
> - *
> - * [32:26] 0 - reserved
> - * [25] 0 - K2FREE: not free running
> - * [24] 0 - K1FREE: not free running
> - * [23] 1 - K0FREE: not free running
> - * [22] 0 - SLFRSH: self refresh disabled
> - * [21] 0 - reserved
> - * [20] 0 - APD: no auto power down
> - * [19] 0 - K2DB2: SDCLK2 is MemClk
> - * [18] 0 - K2RUN: disable SDCLK2
> - * [17] 0 - K1DB2: SDCLK1 is MemClk
> - * [16] 1 - K1RUN: enable SDCLK1
> - * [15] 1 - E1PIN: SDRAM clock enable
> - * [14] 1 - K0DB2: SDCLK0 is MemClk
> - * [13] 0 - K0RUN: disable SDCLK0
> - * [12] 1 - E0PIN: disable SDCKE0
> - * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
> - */
> -#define CONFIG_SYS_MDREFR_VAL 0x0081D018
> -
> -/* MDMRS: Mode Register Set Configuration Register
> - *
> - * [31] 0 - reserved
> - * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
> - * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
> - * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
> - * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
> - * [15] 0 - reserved
> - * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
> - * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
> - * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
> - * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
> - */
> -#define CONFIG_SYS_MDMRS_VAL 0x00020022
> -
> -/*
> - * PCMCIA and CF Interfaces
> - */
> -#define CONFIG_SYS_MECR_VAL 0x00000000
> -#define CONFIG_SYS_MCMEM0_VAL 0x00000000
> -#define CONFIG_SYS_MCMEM1_VAL 0x00000000
> -#define CONFIG_SYS_MCATT0_VAL 0x00000000
> -#define CONFIG_SYS_MCATT1_VAL 0x00000000
> -#define CONFIG_SYS_MCIO0_VAL 0x00000000
> -#define CONFIG_SYS_MCIO1_VAL 0x00000000
> -
> -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
> -#define CONFIG_SYS_SXCNFG_VAL 0x00000000
> -
> -/*
> -#define CSB226_USER_LED0 0x00000008
> -#define CSB226_USER_LED1 0x00000010
> -#define CSB226_USER_LED2 0x00000020
> -*/
> -
> -/*
> - * FLASH and environment organization
> - */
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
> -
> -/* timeout values are in ticks */
> -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
> -
> -#endif /* __CONFIG_H */
> --
> 1.7.6.3
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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