[U-Boot] [PATCH] ARM: Generic cache ops skeleton

[Simon Glass]

Hi Mike,

On Sun, Nov 6, 2011 at 5:09 PM, Mike Frysinger <vapier at gentoo.org> wrote:
> On Sunday 06 November 2011 14:29:47 Simon Glass wrote:
>> On this particular patch, I feel it should be more explicit about L1
>> cache, which is what I think it deals with. We may want to support L2
>> also through a similar API. And a CONFIG option is a good idea.
>
> the point of flushing caches is to make the memory coherent to other devices
> (like peripherals).  we don't differentiate between the cache levels.

Do we not have a situation where the L2 is coherent wrt on-chip
peripherals? I haven't looked into it.

>
>> Finally, even the CP15/cache/MMU code is duplicated in different
>> arch/arm/cpu subdirs. Can we unify this a bit?
>
> things should be separated based on core and system levels.  the fact that a
> particular SoC is say armv4 doesn't mean it should have armv4 specific
> cache/mmu handling in its SoC subdir.  i think the Linux arm tree is properly
> separating things.
> -mike
>

Actually I have this wrong - it was the CP15 stuff I was thinking of
(in start.S). For cache it is just weak functions that are overridden
in the ARMv7 case, and for MMU we only use ARMv4 features.

Going back to this patch, where will cpu_register_cache_ops() be called?

Regards,
Simon