[U-Boot] [PATCH 10/12] OMAP3: Add SPL support to omap3_evm

Igor Grinberg grinberg at compulab.co.il
Tue Nov 8 09:02:38 CET 2011


On 11/08/11 00:03, Tom Rini wrote:
> Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>.  We
> don't calculate the MCFG value here for the Micron parts as the provided
> one assumes a memory size which is incorrect.
> 
> Signed-off-by: Tom Rini <trini at ti.com>
> ---
>  arch/arm/include/asm/arch-omap3/mem.h |   38 +++++++++++++++++++++
>  board/ti/evm/config.mk                |   33 ------------------
>  board/ti/evm/evm.c                    |   42 ++++++++++++++++++++++-
>  include/configs/omap3_evm.h           |   58 +++++++++++++++++++++++++++++++--
>  4 files changed, 133 insertions(+), 38 deletions(-)
>  delete mode 100644 board/ti/evm/config.mk
> 
> diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
> index f467ba9..7b0aaa1 100644
> --- a/arch/arm/include/asm/arch-omap3/mem.h
> +++ b/arch/arm/include/asm/arch-omap3/mem.h
> @@ -60,6 +60,44 @@ enum {
>  #define SDP_SDRC_DLLAB_CTRL	((DLL_ENADLL << 3) | \
>  				(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
>  
> +/* Hynix part of AM/DM37xEVM (200MHz optimized)
> + *   ACTIMA
> + *	TDAL		= 6
> + *	TDPL (Twr)	= 3
> + *	TRRD		= 2
> + *	TRCD		= 4
> + *	TRP		= 3
> + *	TRAS		= 8
> + *	TRC		= 11
> + *	TRFC		= 18
> + *   ACTIMB
> + *	TWTR		= 2
> + *	TCKE		= 1
> + *	TXP		= 1
> + *	TXSR		= 28
> + */
> +#define HYNIX_TDAL_200		6
> +#define HYNIX_TDPL_200		3
> +#define HYNIX_TRRD_200		2
> +#define HYNIX_TRCD_200		4
> +#define HYNIX_TRP_200		3
> +#define HYNIX_TRAS_200		8
> +#define HYNIX_TRC_200		11
> +#define HYNIX_TRFC_200		18
> +#define HYNIX_V_ACTIMA_200	((HYNIX_TRFC_200 << 27) | \
> +		(HYNIX_TRC_200 << 22) | (HYNIX_TRAS_200 << 18) | \
> +		(HYNIX_TRP_200 << 15) |  (HYNIX_TRCD_200 << 12) | \
> +		(HYNIX_TRRD_200 << 9) |  (HYNIX_TDPL_200 << 6) | \
> +		(HYNIX_TDAL_200))
> +
> +#define HYNIX_TWTR_200		2
> +#define HYNIX_TCKE_200		1
> +#define HYNIX_TXP_200		1
> +#define HYNIX_XSR_200		28
> +#define HYNIX_V_ACTIMB_200	(((HYNIX_TCKE_200 << 12) | \
> +		(HYNIX_XSR_200 << 0)) |	(HYNIX_TXP_200 << 8) | \
> +		(HYNIX_TWTR_200 << 16))
> +
>  /* Infineon part of 3430SDP (165MHz optimized) 6.06ns
>   *   ACTIMA
>   *	TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
> diff --git a/board/ti/evm/config.mk b/board/ti/evm/config.mk
> deleted file mode 100644
> index d173eef..0000000
> --- a/board/ti/evm/config.mk
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -#
> -# (C) Copyright 2006 - 2008
> -# Texas Instruments, <www.ti.com>
> -#
> -# EVM uses OMAP3 (ARM-CortexA8) cpu
> -# see http://www.ti.com/ for more information on Texas Instruments
> -#
> -# See file CREDITS for list of people who contributed to this
> -# project.
> -#
> -# This program is free software; you can redistribute it and/or
> -# modify it under the terms of the GNU General Public License as
> -# published by the Free Software Foundation; either version 2 of
> -# the License, or (at your option) any later version.
> -#
> -# This program is distributed in the hope that it will be useful,
> -# but WITHOUT ANY WARRANTY; without even the implied warranty of
> -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -# GNU General Public License for more details.
> -#
> -# You should have received a copy of the GNU General Public License
> -# along with this program; if not, write to the Free Software
> -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> -# MA 02111-1307 USA
> -#
> -# Physical Address:
> -# 8000'0000 (bank0)
> -# A000/0000 (bank1)
> -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
> -# (mem base + reserved)
> -
> -# For use with external or internal boots.
> -CONFIG_SYS_TEXT_BASE = 0x80008000

Does not belong to this patch, is it?

> diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
> index b17c0fb..debf564 100644
> --- a/board/ti/evm/evm.c
> +++ b/board/ti/evm/evm.c
> @@ -1,5 +1,5 @@
>  /*
> - * (C) Copyright 2004-2008
> + * (C) Copyright 2004-2011
>   * Texas Instruments, <www.ti.com>
>   *
>   * Author :
> @@ -119,6 +119,44 @@ int board_init(void)
>  	return 0;
>  }
>  
> +#ifdef CONFIG_SPL_BUILD
> +/*
> + * Routine: get_board_mem_timings
> + * Description: If we use SPL then there is no x-loader nor config header
> + * so we have to setup the DDR timings outself on the first bank.  This
> + * provides the timing values back to the function that configures
> + * the memory.
> + */
> +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
> +		u32 *mr)
> +{
> +	int pop_mfr, pop_id;
> +
> +	/*
> +	 * We need to identify what PoP memory is on the board so that
> +	 * we know what timings to use.  If we can't identify it then
> +	 * we know it's an xM.

This comment should be slightly adjusted, evm is not beagle...

> +	 */
> +	identify_pop_memory(&pop_mfr, &pop_id);
> +
> +	if ((pop_mfr == 0xad) && (pop_id == 0xbc)) {

No need for extra parenthesis.

> +		*ctrla = HYNIX_V_ACTIMA_200;
> +		*ctrlb = HYNIX_V_ACTIMB_200;
> +		*mcfg = 0x03588099;
> +	} else {
> +		*ctrla = MICRON_V_ACTIMA_165;
> +		*ctrlb = MICRON_V_ACTIMB_165;
> +		/*
> +		 * MICRON_V_MCFG_165 would be correct here except that
> +		 * we have 128MB not PHYS_SDRAM_1_SIZE (32MB)
> +		 */
> +		*mcfg = 0x02584099;
> +	}
> +	*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +	*mr = MICRON_V_MR_165;
> +}
> +#endif
> +
>  /*
>   * Routine: misc_init_r
>   * Description: Init ethernet (done here so udelay works)
> @@ -223,7 +261,7 @@ int board_eth_init(bd_t *bis)
>  }
>  #endif /* CONFIG_CMD_NET */
>  
> -#ifdef CONFIG_GENERIC_MMC
> +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
>  int board_mmc_init(bd_t *bis)
>  {
>  	omap_mmc_init(0);
> diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
> index 7a76288..511b599 100644
> --- a/include/configs/omap3_evm.h
> +++ b/include/configs/omap3_evm.h
> @@ -101,9 +101,6 @@
>  #define CONFIG_OMAP_HSMMC		1
>  #define CONFIG_DOS_PARTITION		1
>  
> -/* DDR - I use Micron DDR */
> -#define CONFIG_OMAP3_MICRON_DDR		1
> -
>  /* USB
>   * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
>   * Enable CONFIG_MUSB_UDD for Device functionalities.
> @@ -360,4 +357,59 @@
>  #define CONFIG_BOOTP_HOSTNAME		0x00000004
>  #define CONFIG_BOOTP_BOOTPATH		0x00000010
>  
> +/* Defines for SPL */
> +#define CONFIG_SPL
> +#define CONFIG_SPL_NAND_SIMPLE
> +#define CONFIG_SPL_TEXT_BASE		0x40200800
> +#define CONFIG_SPL_MAX_SIZE		(45 * 1024)	/* 45 KB */
> +#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
> +
> +#define CONFIG_SPL_BSS_START_ADDR	0x80000000
> +#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
> +
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
> +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
> +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
> +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
> +
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBDISK_SUPPORT
> +#define CONFIG_SPL_I2C_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SPL_FAT_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SPL_POWER_SUPPORT
> +#define CONFIG_SPL_NAND_SUPPORT
> +#define CONFIG_SPL_OMAP3_POP_PROBE
> +#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
> +
> +/* NAND boot config */
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_PAGE_COUNT	64
> +#define CONFIG_SYS_NAND_PAGE_SIZE	2048
> +#define CONFIG_SYS_NAND_OOBSIZE		64
> +#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
> +#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
> +#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
> +						10, 11, 12, 13}
> +#define CONFIG_SYS_NAND_ECCSIZE		512
> +#define CONFIG_SYS_NAND_ECCBYTES	3
> +#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
> +						CONFIG_SYS_NAND_ECCSIZE)
> +#define CONFIG_SYS_NAND_ECCTOTAL       (CONFIG_SYS_NAND_ECCBYTES * \
> +						CONFIG_SYS_NAND_ECCSTEPS)
> +#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
> +
> +/*
> + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
> + * 64 bytes before this address should be set aside for u-boot.img's
> + * header. That is 0x800FFFC0--0x80100000 should not be used for any
> + * other needs.
> + */
> +#define CONFIG_SYS_TEXT_BASE		0x80100000
> +#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
> +
>  #endif /* __CONFIG_H */

-- 
Regards,
Igor.


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