[U-Boot] [PATCH v2] MMC: PL180: Fix infinite loop with VExpress extended fifo implementation

[Andy Fleming]

On Fri, Nov 4, 2011 at 8:06 AM, Jon Medhurst (Tixy)
<jon.medhurst at linaro.org> wrote:
> The new IO FPGA implementation for Versatile Express contains an MMCI
> (PL180) cell with the FIFO extended to 128 words. This causes the
> read_bytes() function to go into an infinite loop; as it will wait for
> for the half-full signal (SDI_STA_RXFIFOBR) if there are more than 8
> words remaining (SDI_FIFO_BURST_SIZE), but it won't receive this signal
> once there are fewer than 64 words left to transfer.
>
> One possible fix is to add some build time configuration to change
> SDI_FIFO_BURST_SIZE for the new implementation. However, the problematic
> code only seems to exist as a small performance optimisation, so the
> solution implemented by this patch is to simply remove it. The error
> checking following the loop is also removed as this will be handled by
> code further down the function.
>
> Cc: Andy Fleming <afleming at gmail.com>
> Signed-off-by: Jon Medhurst <jon.medhurst at linaro.org>

Applied, thx