[U-Boot] [PATCH] ARM: FIX for dcache_disable() for ARM926ej-s

[Albert ARIBAUD]

Hi Bas,

Le 04/11/2011 10:40, Bas van den Berg a écrit :
> the cache also needs to be invalidated, not just flushed, Since re-enabling it,
> can cause inconsistent data without invalidation.
>
> Signed-off-by: Bas van den Berg<b.van.den.berg.nl at gmail.com>
> ---
>   arch/arm/lib/cache.c |    2 ++
>   1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
> index b545fb7..10eb8c9 100644
> --- a/arch/arm/lib/cache.c
> +++ b/arch/arm/lib/cache.c
> @@ -37,6 +37,8 @@ void  __flush_cache(unsigned long start, unsigned long size)
>   	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
>   	/* disable write buffer as well (page 2-22) */
>   	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
> +    /* Invalidate dcache as well */
> +    asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
>   #endif
>   	return;
>   }

Come to think of it... NAK, sorry. Flushing should do what it says on 
the tin, and invalidating is not what it says -- especially considering 
your intent is not about flushing but about disabling ('re-enabling...')

If you need the cache to be flushed then invalidated then disabled, then 
call all three functions where you need that, i.e. find the place where 
there is only a call to __flush_cache() and append a call to 
__invalidate_cache(), and if that happens a lot, then feel free to 
provide a new function that will sequence flush and invalidate.

Amicalement,
-- 
Albert.