[U-Boot] [PATCH v3 05/12] OMAP3: Add optimal SDRC autorefresh control values

[Heiko Schocher]

Hello Tom,

Tom Rini wrote:
> This adds the optimal SDRC autorefresh control register values for
> 100Mhz, 133MHz, 165MHz and 200MHz clocks.  We switch to using this
> to provide the default 165MHz value.
> 
> Signed-off-by: Tom Rini <trini at ti.com>
> ---
>  arch/arm/include/asm/arch-omap3/mem.h |   12 +++++++-----
>  1 files changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
> index db6a696..9775b59 100644
> --- a/arch/arm/include/asm/arch-omap3/mem.h
> +++ b/arch/arm/include/asm/arch-omap3/mem.h
> @@ -43,6 +43,12 @@ enum {
>  #define SDRC_SHARING	0x00000100
>  #define SDRC_MR_0_SDR	0x00000031
>  
> +/* optimized timings good for current shipping parts */
> +#define SDP_3430_SDRC_RFR_CTRL_100MHz	0x0002da01
> +#define SDP_3430_SDRC_RFR_CTRL_133MHz	0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
> +#define SDP_3430_SDRC_RFR_CTRL_165MHz	0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
> +#define SDP_3430_SDRC_RFR_CTRL_200MHz	0x0005e601 /* 7.8us/5ns - 50=0x5e6 */

You should use something like that here:

#define OMAP3_SDP_SDRC_xx_SHIFT	8
#define OMAP3_SDP_SDRC_yy	(1 << 0)

#define SDP_3430_SDRC_RFR_CTRL_200MHz ((0x5e6 << OMAP3_SDP_SDRC_xx_SHIFT) |
					OMAP3_SDP_SDRC_yy)

of course with the right "names" for xx and yy, I have not
the cpu doc at hand actual.

bye,
Heiko
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