[U-Boot] Patches for SMSC LAN911X driver on UBoot and QEMU

[Cachet Bertrand]

Hi,

I have made some modification to the SMSC LAN911X driver for both UBoot and QEMU in order to be able to use SMSC LAN9X based network drivers during the u-boot stage.


1)      U-Boot
In UBoot, when the LAN911X device is reseted, the READY bit is checked and device is wake up by writing onto the TEST_BYTE register if the READY bit cleared (0b). But from the datasheet of the SMSC LAN9118/LAN9115/LAN9220 in the section Power Management (3.10), it is said that READY bit is cleared when PM_MODE is set to D1 or D2 and set only when in D0 mode.

3.10.2
Functional Description
There is one normal operating power state, D0 and there are two power saving states: D1, and D2.
Upon entry into either of the two power saving states, only the PMT_CTRL register is accessible for
read operations. In either of the power saving states the READY bit in the PMT_CTRL register will be
cleared. Reads of any other addresses are forbidden until the READY bit is set. All writes, with the
exception of the wakeup write to BYTE_TEST, are also forbidden until the READY bit is set. Only when
in the D0 (Normal) state, when the READY bit is set, can the rest of the device be accessed.

So I modified the code (drivers/net/smc911x.h) to wake up the device only if the READY bit is cleared (0b). If it is set (1b) then we just do nothing.

Patch is contained in following commit : https://bitbucket.org/bca/u-boot-linaro-stable/changeset/b870326105da


2)      QEMU
In the driver for the SMSC LAN9118 device (hw/lan9118.c), I modify the code to update the PM_CTRL register (switch PM_MODE bits to D0 and set (1b) READY bit ) when writing to the BYTE_TEST register.

Writing to PM_CTRL was not permitted before this modification => raise an harware error => QEMU crash when happen. So when you try to perform network connection in u-boot stage in QEMU, QEMU crashed.

Patch is contained in the following commit : https://bitbucket.org/bca/qemu-linaro/changeset/0aa1f76e5141


If you have any question, or if you find any mistake in my understanding, please feel free to contact me.

Hope it helps others and a bit thanks for the Linaro initiative

--
Bertrand Cachet, Ingénieur CPE (Lyon, France)
Institut REDS, Reconfigurable & Embedded Digital Systems

Tél     : +41 24/55 77 372
Email   : bertrand.cachet at heig-vd.ch<mailto:bertrand.cachet at heig-vd.ch>
Internet: http://www.reds.ch

HEIG-VD, Haute Ecole d'Ingénierie et de Gestion du Canton de Vaud
Rte de Cheseaux 1
CH-1401 Yverdon-les-Bains
Internet: http://www.heig-vd.ch