[U-Boot] [PATCH 2/6] i.mx: Add the initial support for freescale i.MX6Q processor
Stefano Babic
sbabic at denx.de
Mon Nov 14 10:03:54 CET 2011
On 11/12/2011 11:36 AM, Jason Liu wrote:
> i.MX6Q is freescale quad core processors with ARM cortex_a9 complex.
> This patch is to add the initial support for this processor.
>
> Signed-off-by: Jason Liu <jason.hui at linaro.org>
> ---
> arch/arm/cpu/armv7/mx6/Makefile | 48 +
> arch/arm/cpu/armv7/mx6/clock.c | 388 +++++++
> arch/arm/cpu/armv7/mx6/iomux-v3.c | 76 ++
> arch/arm/cpu/armv7/mx6/lowlevel_init.S | 60 +
> arch/arm/cpu/armv7/mx6/soc.c | 57 +
> arch/arm/include/asm/arch-mx6/ccm_regs.h | 894 +++++++++++++++
> arch/arm/include/asm/arch-mx6/clock.h | 50 +
> arch/arm/include/asm/arch-mx6/gpio.h | 35 +
> arch/arm/include/asm/arch-mx6/imx-regs.h | 233 ++++
> arch/arm/include/asm/arch-mx6/iomux-v3.h | 104 ++
> arch/arm/include/asm/arch-mx6/mx6x_pins.h | 1683 +++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-mx6/sys_proto.h | 38 +
> 12 files changed, 3666 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
> new file mode 100644
> index 0000000..b0da028
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/mx6/Makefile
> @@ -0,0 +1,48 @@
> +#
> +# (C) Copyright 2000-2006
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# (C) Copyright 2011 Freescale Semiconductor, Inc.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(SOC).o
> +
> +COBJS = soc.o clock.o iomux-v3.o
> +SOBJS = lowlevel_init.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
> +
> +all: $(obj).depend $(LIB)
> +
> +$(LIB): $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
> new file mode 100644
> index 0000000..e0d9c6f
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -0,0 +1,388 @@
> +/*
> + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/errno.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/ccm_regs.h>
> +#include <asm/arch/clock.h>
> +
> +enum pll_clocks {
> + PLL_SYS, /* System PLL */
> + PLL_BUS, /* System Bus PLL*/
> + PLL_USBOTG, /* OTG USB PLL */
> + PLL_ENET, /* ENET PLL */
> +};
> +
> +struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
> +
> +static u32 decode_pll(enum pll_clocks pll, u32 infreq)
> +{
> + u32 div;
> +
> + switch (pll) {
> + case PLL_SYS:
> + div = __raw_readl(&imx_ccm->analog_pll_sys);
> + div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
> +
> + return infreq * (div >> 1);
> + case PLL_BUS:
> + div = __raw_readl(&imx_ccm->analog_pll_528);
> + div &= BM_ANADIG_PLL_528_DIV_SELECT;
> +
> + return infreq * (20 + (div << 1));
> + case PLL_USBOTG:
> + div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
> + div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
> +
> + return infreq * (20 + (div << 1));
> + case PLL_ENET:
> + div = __raw_readl(&imx_ccm->analog_pll_enet);
> + div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
> +
> + return (div == 3 ? 125000000 : 25000000 * (div << 1));
> + default:
> + return 0;
> + }
> + /* NOTREACHED */
> +}
> +
> +static u32 get_mcu_main_clk(void)
> +{
> + u32 reg, freq;
> +
> + reg = __raw_readl(&imx_ccm->cacrr);
> + reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
> + reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
> + freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
> +
> + return freq / (reg + 1);
> +}
> +
> +static u32 get_periph_clk(void)
> +{
> + u32 reg, freq = 0;
> +
> + reg = __raw_readl(&imx_ccm->cbcdr);
> + if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
> + reg = __raw_readl(&imx_ccm->cbcmr);
> + reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
> + reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
> +
> + switch (reg) {
> + case 0:
> + freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
> + break;
> + case 1:
> + case 2:
> + freq = CONFIG_SYS_MX6_HCLK;
> + break;
> + default:
> + break;
> + }
> + } else {
> + reg = __raw_readl(&imx_ccm->cbcmr);
> + reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
> + reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
> +
> + switch (reg) {
> + case 0:
> + freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
> + break;
> + case 1:
> + freq = PLL2_PFD2_FREQ;
> + break;
> + case 2:
> + freq = PLL2_PFD0_FREQ;
> + break;
> + case 3:
> + freq = PLL2_PFD2_DIV_FREQ;
> + break;
> + default:
> + break;
> + }
> + }
> +
> + return freq;
> +}
> +
> +
> +static u32 get_ahb_clk(void)
> +{
> + u32 reg, ahb_podf;
> +
> + reg = __raw_readl(&imx_ccm->cbcdr);
> + reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
> + ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
> +
> + return get_periph_clk() / (ahb_podf + 1);
> +}
> +
> +static u32 get_ipg_clk(void)
> +{
> + u32 reg, ipg_podf;
> +
> + reg = __raw_readl(&imx_ccm->cbcdr);
> + reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
> + ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
> +
> + return get_ahb_clk() / (ipg_podf + 1);
> +}
> +
> +static u32 get_ipg_per_clk(void)
> +{
> + u32 reg, perclk_podf;
> +
> + reg = __raw_readl(&imx_ccm->cscmr1);
> + perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
> +
> + return get_ipg_clk() / (perclk_podf + 1);
> +}
> +
> +static u32 get_uart_clk(void)
> +{
> + u32 reg, uart_podf;
> +
> + reg = __raw_readl(&imx_ccm->cscdr1);
> + reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
> + uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
> +
> + return PLL3_80M / (uart_podf + 1);
> +}
> +
> +
> +static u32 get_cspi_clk(void)
> +{
> + u32 reg, cspi_podf;
> +
> + reg = __raw_readl(&imx_ccm->cscdr2);
> + reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
> + cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
> +
> + return PLL3_60M / (cspi_podf + 1);
> +}
> +
> +static u32 get_axi_clk(void)
> +{
> + u32 root_freq, axi_podf;
> + u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
> +
> + axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
> + axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
> +
> + if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
> + if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
> + root_freq = PLL2_PFD2_FREQ;
> + else
> + root_freq = PLL3_PFD1_FREQ;;
> + } else
> + root_freq = get_periph_clk();
> +
> + return root_freq / (axi_podf + 1);
> +}
> +
> +static u32 get_emi_slow_clk(void)
> +{
> + u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
> +
> + cscmr1 = __raw_readl(&imx_ccm->cscmr1);
> + emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
> + emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
> + emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
> + emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
> +
> + switch (emi_clk_sel) {
> + case 0:
> + root_freq = get_axi_clk();
> + break;
> + case 1:
> + root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
> + break;
> + case 2:
> + root_freq = PLL2_PFD2_FREQ;
> + break;
> + case 3:
> + root_freq = PLL2_PFD0_FREQ;
> + break;
> + }
> +
> + return root_freq / (emi_slow_pof + 1);
> +}
> +
> +static u32 get_mmdc_ch0_clk(void)
> +{
> + u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
> + u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
> + MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
> +
> + return get_periph_clk() / (mmdc_ch0_podf + 1);
> +}
> +
> +static u32 get_usdhc1_clk(void)
> +{
> + u32 root_freq = 0;
> + u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
> + u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
> + u32 usdhc1_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
> + MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
> +
> + if (cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL)
> + root_freq = PLL2_PFD0_FREQ;
> + else
> + root_freq = PLL2_PFD2_FREQ;
> +
> + return root_freq / (usdhc1_podf + 1);
> +}
> +
> +static u32 get_usdhc2_clk(void)
> +{
> + u32 root_freq = 0;
> + u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
> + u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
> + u32 usdhc2_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
> + MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
> +
> + if (cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL)
> + root_freq = PLL2_PFD0_FREQ;
> + else
> + root_freq = PLL2_PFD2_FREQ;
> +
> + return root_freq / (usdhc2_podf + 1);
> +}
> +
> +static u32 get_usdhc3_clk(void)
> +{
> + u32 root_freq = 0;
> + u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
> + u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
> + u32 usdhc3_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
> + MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
> +
> + if (cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL)
> + root_freq = PLL2_PFD0_FREQ;
> + else
> + root_freq = PLL2_PFD2_FREQ;
> +
> + return root_freq / (usdhc3_podf + 1);
> +}
> +
> +static u32 get_usdhc4_clk(void)
> +{
> + u32 root_freq = 0;
> + u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
> + u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
> + u32 usdhc4_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
> + MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
> +
> + if (cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL)
> + root_freq = PLL2_PFD0_FREQ;
> + else
> + root_freq = PLL2_PFD2_FREQ;
> +
> + return root_freq / (usdhc4_podf + 1);
> +}
All get_usdhcX function are identical, except for two masks
(MXC_CCM_CSCDR1_USDHCx_PODF_MASK and MXC_CCM_CSCMR1_USDHCx_CLK_SEL).
Merge them in a get_usdhc_clk(usdhc_number)
> diff --git a/arch/arm/cpu/armv7/mx6/iomux-v3.c b/arch/arm/cpu/armv7/mx6/iomux-v3.c
> new file mode 100644
> index 0000000..ff934ea
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/mx6/iomux-v3.c
> @@ -0,0 +1,76 @@
> +/*
> + * Based on the iomux-v3.c from Linux kernel:
> + * Copyright (C) 2008 by Sascha Hauer <kernel at pengutronix.de>
> + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
> + * <armlinux at phytec.de>
> + *
> + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301, USA.
> + */
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/mx6x_pins.h>
> +#include <asm/arch/iomux-v3.h>
> +
> +static void *base;
> +
> +/*
> + * configures a single pad in the iomuxer
> + */
> +int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
> +{
> + u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
> + u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
> + u32 sel_input_ofs =
> + (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
> + u32 sel_input =
> + (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
> + u32 pad_ctrl_ofs =
> + (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
> + u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
> +
> + if (mux_ctrl_ofs)
> + __raw_writel(mux_mode, base + mux_ctrl_ofs);
> +
> + if (sel_input_ofs)
> + __raw_writel(sel_input, base + sel_input_ofs);
> +
> + if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
> + __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
> +
> + return 0;
> +}
> +
> +int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
> +{
> + iomux_v3_cfg_t *p = pad_list;
> + int i;
> + int ret;
> +
> + for (i = 0; i < count; i++) {
> + ret = imx_iomux_v3_setup_pad(*p);
> + if (ret)
> + return ret;
> + p++;
> + }
> + return 0;
> +}
> +
> +void imx_iomux_v3_init(void *iomux_v3_base)
> +{
> + base = iomux_v3_base;
> +}
> +#if defined(CONFIG_FEC_MXC)
> +void imx_get_mac_from_fuse(unsigned char *mac)
> +{
> + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
> + struct fuse_bank *bank = &iim->bank[4];
> + struct fuse_bank4_regs *fuse =
> + (struct fuse_bank4_regs *)bank->fuse_regs;
> +
> + u32 mac_lo = readl(&fuse->mac_addr_low);
> + u32 mac_hi = readl(&fuse->mac_addr_high);
> +
> + *(u32 *)mac = mac_lo;
> +
> + mac[4] = mac_hi & 0xff;
> + mac[5] = (mac_hi >> 8) & 0xff;
> +
> +}
Even if the implementation is slightly different, this function (except
for the bank number) does the same things for MX5 and MX6 - you can als
put it into imx-common.
> +#endif
> diff --git a/arch/arm/include/asm/arch-mx6/ccm_regs.h b/arch/arm/include/asm/arch-mx6/ccm_regs.h
> new file mode 100644
> index 0000000..e8f0a93
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx6/ccm_regs.h
> @@ -0,0 +1,894 @@
> +/*
> + * Freescale ANADIG Register Definitions
> + *
> + * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
> +#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
> +
> +struct imx_ccm_reg {
> + u32 ccr; /* 0x0000 */
> + u32 ccdr;
> + u32 csr;
> + u32 ccsr;
> + u32 cacrr; /* 0x0010*/
> + u32 cbcdr;
> + u32 cbcmr;
> + u32 cscmr1;
> + u32 cscmr2; /* 0x0020 */
> + u32 cscdr1;
> + u32 cs1cdr;
> + u32 cs2cdr;
> + u32 cdcdr; /* 0x0030 */
> + u32 chscdr;
> + u32 cscdr2;
> + u32 cscdr3;
> + u32 cscdr4; /* 0x0040 */
> + u32 resv0;
> + u32 cdhipr;
> + u32 cdcr;
> + u32 ctor; /* 0x0050 */
> + u32 clpcr;
> + u32 cisr;
> + u32 cimr;
> + u32 ccosr; /* 0x0060 */
> + u32 cgpr;
> + u32 CCGR0;
> + u32 CCGR1;
> + u32 CCGR2; /* 0x0070 */
> + u32 CCGR3;
> + u32 CCGR4;
> + u32 CCGR5;
> + u32 CCGR6; /* 0x0080 */
> + u32 CCGR7
Checking this there something confusing in actual code. There is struct
mxc_ccm_reg in crm_regs.h and struct clkctl in imx-regs.h. The two
structure are identical. I am asking myself why...it seems to me that
someting went wrong.
If there is no evident reason, we should even clean up this point.
And it is better you use one of the already supplied names (mxc_ccm_reg
or clkctl), without adding a new one.
> diff --git a/arch/arm/include/asm/arch-mx6/gpio.h b/arch/arm/include/asm/arch-mx6/gpio.h
> new file mode 100644
> index 0000000..1dc34e9
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx6/gpio.h
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright (C) 2011
> + * Stefano Babic, DENX Software Engineering, <sbabic at denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +
> +#ifndef __ASM_ARCH_MX5_GPIO_H
> +#define __ASM_ARCH_MX5_GPIO_H
> +
> +/* GPIO registers */
> +struct gpio_regs {
> + u32 gpio_dr;
> + u32 gpio_dir;
> + u32 gpio_psr;
> +};
> +
> +#endif
Maybe do we find a way to add a common include directory ? This file is
duplicated. We can use include/asm/arch/imx-common
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
More information about the U-Boot
mailing list