[U-Boot] [RFC PATCH v2 10/12] arm, da850evm: Add an SPL for SPI boot

[Christian Riesch]

Signed-off-by: Christian Riesch <christian.riesch at omicron.at>
Cc: Heiko Schocher <hs at denx.de>
Cc: Sandeep Paulraj <s-paulraj at ti.com>
Cc: Sudhakar Rajashekhara <sudhakar.raj at ti.com>
---
 board/davinci/da8xxevm/u-boot-spl.lds |   73 +++++++++++++++++++++++++++++++++
 include/configs/da850evm.h            |   53 +++++++++++++++++++++++-
 2 files changed, 125 insertions(+), 1 deletions(-)
 create mode 100644 board/davinci/da8xxevm/u-boot-spl.lds

diff --git a/board/davinci/da8xxevm/u-boot-spl.lds b/board/davinci/da8xxevm/u-boot-spl.lds
new file mode 100644
index 0000000..6f6e065
--- /dev/null
+++ b/board/davinci/da8xxevm/u-boot-spl.lds
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj at denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg at denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	__start = .;
+	  arch/arm/cpu/arm926ejs/start.o	(.text)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	} >.sram
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	} >.sram
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sram
+
+	__image_copy_end = .;
+	_end = .;
+}
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 4c14370..517e2ef 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -29,7 +29,6 @@
 #define CONFIG_DRIVER_TI_EMAC
 #define CONFIG_USE_SPIFLASH
 
-
 /*
  * SoC Configuration
  */
@@ -64,6 +63,41 @@
 #define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
 #define CONFIG_STACKSIZE	(256*1024) /* regular stack */
 
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ((1 << 27) | (1 << 22) | (1 << 20) | \
+					 (1 << 5) | (1 << 16))
+
+/*
+ * PLL configuration
+ */
+#define CONFIG_SYS_DV_CLKMODE          0
+#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
+
+#define CONFIG_SYS_DA850_PLL0_PLLM     24
+#define CONFIG_SYS_DA850_PLL1_PLLM     21
+
+/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR 0x000000C4
+#define CONFIG_SYS_DA850_DDR2_SDBCR    0x0A034622
+#define CONFIG_SYS_DA850_DDR2_SDBCR2   0x00000000
+#define CONFIG_SYS_DA850_DDR2_SDTIMR   0x184929C8
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2  0xB80FC700
+#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000406
+#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+
 /*
  * Serial Driver info
  */
@@ -75,6 +109,7 @@
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2
 
 #define CONFIG_SPI
 #define CONFIG_SPI_FLASH
@@ -241,8 +276,24 @@
 #undef CONFIG_CMD_ENV
 #endif
 
+/* defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LDSCRIPT	"$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_STACK	0x8001ff00
+#define CONFIG_SPL_TEXT_BASE	0x80000000
+#define CONFIG_SPL_MAX_SIZE	(20<<10)
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
+
 /* additions for new relocation code, must added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		0xc0000000
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 					GENERATED_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */
-- 
1.7.0.4