[U-Boot] [PATCH 04/11] MIPS: add register definition for EBase register
Marek Vasut
marek.vasut at gmail.com
Fri Nov 25 09:43:46 CET 2011
> The CPUNum field in the Ebase register contains an unique identifier
> for each CPU. This helps to distinguish between CPU cores in
> multi-processor systems.
>
> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck at googlemail.com>
> ---
> arch/mips/include/asm/mipsregs.h | 13 +++++++++++++
> 1 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/include/asm/mipsregs.h
> b/arch/mips/include/asm/mipsregs.h index be7e5c6..15a9fd5 100644
> --- a/arch/mips/include/asm/mipsregs.h
> +++ b/arch/mips/include/asm/mipsregs.h
> @@ -89,6 +89,13 @@
> #define CP0_DWATCH $19
>
> /*
> + * Additional Coprocessor 0 register names.
> + * These registers are listed for completeness and are intended
> + * for usage in assembly code.
> + */
> +#define CP0_EBASE $15,1
> +
> +/*
> * Coprocessor 0 Set 1 register names
> */
> #define CP0_S1_DERRADDR0 $26
> @@ -395,6 +402,12 @@
> #define CAUSEF_BD (_ULCAST_(1) << 31)
>
> /*
> + * Bits in the coprocessor 0 EBase register.
> + */
> +#define EBASEB_CPUNUM 0
> +#define EBASEF_CPUNUM (_ULCAST_(1023))
What's this? Isn't the maximum CPU number on MIPS 32 CPUs? Or maybe that's only
4kc limit?
> +
> +/*
> * Bits in the coprocessor 0 config register.
> */
> /* Generic bits. */
M
More information about the U-Boot
mailing list