[U-Boot] [PATCH 05/11] MIPS: add sleep handler for slave CPUs in multi-processor systems

[Daniel Schwierzeck]

On Mon, Nov 28, 2011 at 5:24 PM, Shinya Kuribayashi <skuribay at pobox.com> wrote:
> On 11/24/11 10:57 PM, Daniel Schwierzeck wrote:
>>
>> diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
>> index 9c1b2f7..b6cb4be 100644
>> --- a/arch/mips/cpu/mips32/start.S
>> +++ b/arch/mips/cpu/mips32/start.S
>> @@ -224,6 +224,14 @@ reset:
>>
>>        setup_c0_status_reset
>>
>> +       /* Set all slave CPUs in sleep mode */
>> +#ifdef CONFIG_SYS_MPS_SLAVE_CPU_SLEEP
>> +       mfc0    k0, CP0_EBASE
>> +       and     k0, EBASEF_CPUNUM
>> +       bne     k0, zero, slave_cpu_sleep
>> +        nop
>> +#endif
>> +
>>        /* Init Timer */
>>        mtc0    zero, CP0_COUNT
>>        mtc0    zero, CP0_COMPARE
>
> Just wondered, why is this conditionally selected?  To save text size,
> or other reason?
>
> The change looks Ok with s/MPS/MIPS/ typo fixed as pointed by Andrew.
>

the patch is relevant only for Lantiq XWAY Danube SoCs which have two 24KC cores
and is ported from Lantiq BSPs.
Actually the internal BootROM already handles the second CPU core.
This code is only
executed, if the board boots from parallel NOR flash without involving
the BootROM. This
is selectable by pin-strapping. But in this mode the second CPU needs
some additonal handling.

So please ignore this patch for the current series. I'll send another
one in the upcoming
Danube SoC support series. Thanks.

-- 
Best regards,
Daniel