[U-Boot] [PATCH 0/5] Add cache line alignment support

[Anton Staaf]

The cache line alignment issue has gone around a couple of times now.  This
patch set implements all of the details that we have discussed about the
implementation of ALLOC_CACHE_ALIGN_BUFFER other than the switch to the Linux
style L1_CACHE_BYTES, L1_CACHE_SHIFT, and ARCH_DMA_MINALIGN defines mentioned
by Mike Frysinger.  It also includes patches that use the macro to fix MMC
and ext2 buffers, as well as define the CONFIG_SYS_CACHELINE_SIZE value for
Tegra and add a default value for CONFIG_SYS_CACHELINE_SIZE with a warning if
it is used.

About the Linux defines that Mike suggests.  It may make sense to move these
patches over to use that mechanism, especially since there are only a few
configs that define CONFIG_SYS_CACHELINE_SIZE anyway.  Also, since this is an
architecture specific parameter and not a board specific one it makes sense
that these configs would be architecture specific.  I am also not supper happy
with the fact that most boards generate a warning with this patchset, because
they don't set CONFIG_SYS_CACHELINE_SIZE.  But I'm not sure that silently
providing a default is a good idea.

I think we can discuss the relative merrits of that move independently of the
implementation of this fix though, and I wanted to get this discussion going
again.

Thanks,
    Anton

---

Anton Staaf (5):
  cache: add ALLOC_CACHE_ALIGN_BUFFER macro
  cache: add default setting for CONFIG_SYS_CACHELINE_SIZE
  tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra
  mmc: dcache: allocate cache aligned buffer for scr and switch_status
  ext2: Cache line aligned partial sector bounce buffer

 doc/README.arm-caches           |    2 +
 drivers/mmc/mmc.c               |   10 +++---
 fs/ext2/dev.c                   |    2 +-
 include/common.h                |   67 +++++++++++++++++++++++++++++++++++++++
 include/configs/tegra2-common.h |    2 +
 5 files changed, 77 insertions(+), 6 deletions(-)

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1.7.3.1