[U-Boot] [PATCH 1/2] Tegra2: Make XTal speed configurable

[Simon Glass]

Hi Marek,

On Fri, Sep 30, 2011 at 5:12 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> The Toradex T20 module uses 13MHz Xtal, so make the Xtal speed configurable.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> Cc: Simon Glass <sjg at chromium.org>
> Cc: Ben Warren <biggerbadderben at gmail.com>
> Cc: Tom Warren <twarren.nvidia at gmail.com>
> Cc: Stephen Warren <swarren at nvidia.com>
> ---
>  arch/arm/cpu/armv7/tegra2/ap20.c |    9 +++++++--
>  1 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
> index dc5f984..71d9f26 100644
> --- a/arch/arm/cpu/armv7/tegra2/ap20.c
> +++ b/arch/arm/cpu/armv7/tegra2/ap20.c
> @@ -31,6 +31,11 @@
>  #include <asm/arch/scu.h>
>  #include <common.h>
>
> +/* The default XTal is 12MHz, some boards might use 13MHz one though */
> +#ifndef        CONFIG_SYS_TEGRA2_XTAL_MHZ
> +#define        CONFIG_SYS_TEGRA2_XTAL_MHZ      12
> +#endif
> +
>  u32 s_first_boot = 1;
>
>  void init_pllx(void)
> @@ -46,8 +51,8 @@ void init_pllx(void)
>        /* Set PLLX_MISC */
>        writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
>
> -       /* Use 12MHz clock here */
> -       reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
> +       /* Use 13MHz clock here */

Change comment?

> +       reg = PLL_BYPASS_MASK | (CONFIG_SYS_TEGRA2_XTAL_MHZ << PLL_DIVM_SHIFT);
>        reg |= 1000 << PLL_DIVN_SHIFT;
>        writel(reg, &pll->pll_base);
>
> --
> 1.7.5.4
>
>

Regards,
Simon