[U-Boot] [PATCH v2 1/1] OMAP3 SPL: Rework memory initalization and devkit 8000 support
Tom Rini
trini at ti.com
Fri Oct 7 02:12:46 CEST 2011
This changes to making the board be responsible for providing a
memory initialization function for SPL and converts the existing
function to provide these services for devkit 8000. As part of this
suffix the Micron DDR settings with their speed.
Cc: Frederik Kriewitz <frederik at kriewitz.eu>
Signed-off-by: Tom Rini <trini at ti.com>
---
arch/arm/cpu/armv7/omap3/sdrc.c | 49 ++++++++++-----------------
arch/arm/include/asm/arch-omap3/mem.h | 42 ++++------------------
arch/arm/include/asm/arch-omap3/sys_proto.h | 1 +
board/timll/devkit8000/devkit8000.c | 25 ++++++++++++++
4 files changed, 52 insertions(+), 65 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 0dd1955..fd26616 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -111,13 +111,24 @@ u32 get_sdr_cs_offset(u32 cs)
/*
* do_sdrc_init -
* - Initialize the SDRAM for use.
- * - code called once in C-Stack only context for CS0 and a possible 2nd
- * time depending on memory configuration from stack+global context
+ * - Code called once in C-Stack only context for CS0 and with early being
+ * true and a possible 2nd time depending on memory configuration from
+ * stack+global context.
*/
void do_sdrc_init(u32 cs, u32 early)
{
- struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
+ struct sdrc_actim *sdrc_actim_base0;
+ struct sdrc_actim *sdrc_actim_base1;
+ sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+ sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+
+ /*
+ * When called in the early context this may be SPL and we will
+ * need to set all of the timings. This ends up being board
+ * specific so we call a helper function to take care of this
+ * for us.
+ */
if (early) {
/* reset sdrc controller */
writel(SOFTRESET, &sdrc_base->sysconfig);
@@ -128,40 +139,18 @@ void do_sdrc_init(u32 cs, u32 early)
/* setup sdrc to ball mux */
writel(SDRC_SHARING, &sdrc_base->sharing);
- /* Disable Power Down of CKE cuz of 1 CKE on combo part */
+ /* Disable Power Down of CKE because of 1 CKE on combo part */
writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
&sdrc_base->power);
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
- }
-/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
- * to prevent this to be build in non-SPL build */
#ifdef CONFIG_SPL_BUILD
- /* If we use a SPL there is no x-loader nor config header so we have
- * to do the job ourselfs
- */
- if (cs == CS0) {
- sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-
- /* General SDRC config */
- writel(V_MCFG, &sdrc_base->cs[cs].mcfg);
- writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl);
-
- /* AC timings */
- writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla);
- writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
-
- /* Initialize */
- writel(CMD_NOP, &sdrc_base->cs[cs].manual);
- writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-
- writel(V_MR, &sdrc_base->cs[cs].mr);
- }
+ /* setup timings */
+ board_early_sdrc_init(sdrc_base, sdrc_actim_base0);
#endif
+ }
/*
* SDRC timings are set up by x-load or config header
@@ -170,8 +159,6 @@ void do_sdrc_init(u32 cs, u32 early)
* configure CS1 to handle this ommission
*/
if (cs == CS1) {
- sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
- sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
writel(readl(&sdrc_base->cs[CS0].mcfg),
&sdrc_base->cs[CS1].mcfg);
writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 8e28f77..9e86d64 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -138,15 +138,15 @@ enum {
#define MICRON_CASWIDTH 0x5
#define MICRON_RASWIDTH 0x2
#define MICRON_LOCKSTATUS 0x0
-#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \
- (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \
- (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \
- (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \
- (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
+#define MICRON_V_MCFG_165 ((MICRON_LOCKSTATUS << 30) | \
+ (MICRON_RASWIDTH << 24) | (MICRON_CASWIDTH << 20) | \
+ (MICRON_ADDRMUXLEGACY << 19) | (MICRON_RAMSIZE << 8) | \
+ (MICRON_BANKALLOCATION << 6) | (MICRON_B32NOT16 << 4) | \
+ (MICRON_DEEPPD << 3) | (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
-#define MICRON_ARCV 2030
-#define MICRON_ARE 0x1
-#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE))
+#define MICRON_ARCV_165 0x4e2
+#define MICRON_ARE 0x1
+#define MICRON_V_RFR_CTRL_165 ((MICRON_ARCV_165 << 8) | (MICRON_ARE))
#define MICRON_BL 0x2
#define MICRON_SIL 0x0
@@ -194,32 +194,6 @@ enum {
(NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \
(NUMONYX_TWTR_165 << 16))
-#ifdef CONFIG_OMAP3_INFINEON_DDR
-#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
-#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
-#endif
-
-#ifdef CONFIG_OMAP3_MICRON_DDR
-#define V_ACTIMA_165 MICRON_V_ACTIMA_165
-#define V_ACTIMB_165 MICRON_V_ACTIMB_165
-#define V_MCFG MICRON_V_MCFG
-#define V_RFR_CTRL MICRON_V_RFR_CTRL
-#define V_MR MICRON_V_MR
-#endif
-
-#ifdef CONFIG_OMAP3_NUMONYX_DDR
-#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
-#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
-#endif
-
-#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
-#error "Please choose the right DDR type in config header"
-#endif
-
-#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL))
-#error "Please choose the right DDR type in config header"
-#endif
-
/*
* GPMC settings -
* Definitions is as per the following format
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 7b60051..7f2631e 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -38,6 +38,7 @@ void per_clocks_enable(void);
void memif_init(void);
void sdrc_init(void);
void do_sdrc_init(u32, u32);
+void board_early_sdrc_init(struct sdrc *, struct sdrc_actim *);
void emif4_init(void);
void gpmc_init(void);
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index f50d113..9a0f657 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -138,3 +138,28 @@ int board_eth_init(bd_t *bis)
return dm9000_initialize(bis);
}
#endif
+
+/*
+ * Routine: board_early_sdrc_init
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings outself on the first bank.
+ */
+void board_early_sdrc_init(struct sdrc *sdrc_base, struct sdrc_actim
+ *sdrc_actim_base0)
+{
+ /* General SDRC config */
+ writel(MICRON_V_MCFG_165, &sdrc_base->cs[CS0].mcfg);
+ writel(MICRON_V_RFR_CTRL_165, &sdrc_base->cs[CS0].rfr_ctrl);
+
+ /* AC timings */
+ writel(MICRON_V_ACTIMA_165, &sdrc_actim_base0->ctrla);
+ writel(MICRON_V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
+
+ /* Initialize */
+ writel(CMD_NOP, &sdrc_base->cs[CS0].manual);
+ writel(CMD_PRECHARGE, &sdrc_base->cs[CS0].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[CS0].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[CS0].manual);
+
+ writel(MICRON_V_MR, &sdrc_base->cs[CS0].mr);
+}
--
1.7.0.4
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