[U-Boot] [PATCH 8/9 v2] powerpc/mpc8548cds: Fix config according to system address map
Zhao Chenhui
chenhui.zhao at freescale.com
Sat Oct 8 09:33:33 CEST 2011
From: chenhui zhao <chenhui.zhao at freescale.com>
- Fix config according to system address map in the manual.
- Rework tlb and law tables.
- Remove unnecessary macros.
Signed-off-by: Zhao Chenhui <chenhui.zhao at freescale.com>
---
Changes for v2:
- Fixed typo in the comments of tlb.c
board/freescale/mpc8548cds/law.c | 19 +++++----
board/freescale/mpc8548cds/mpc8548cds.c | 8 ++--
board/freescale/mpc8548cds/tlb.c | 67 ++++++++++++++++---------------
include/configs/MPC8548CDS.h | 56 ++++++++++++-------------
4 files changed, 76 insertions(+), 74 deletions(-)
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index 5b6943d..f0de509 100644
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c
@@ -31,13 +31,14 @@
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0x8000_0000 0x8fff_ffff PCI1 MEM 256M
+ * 0x9000_0000 0x9fff_ffff PCI2 MEM 256M
* 0xa000_0000 0xbfff_ffff PCIe MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
- * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
- * 0xe300_0000 0xe30f_ffff PCIe IO 1M
+ * 0xe000_0000 0xe00f_ffff CCSR 1M
+ * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
+ * 0xe280_0000 0xe2ff_ffff PCI2 IO 8M
+ * 0xe300_0000 0xe3ff_ffff PCIe IO 16M
* 0xf000_0000 0xf3ff_ffff SDRAM 64M
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
@@ -52,11 +53,11 @@
struct law_entry law_table[] = {
#ifdef CONFIG_SYS_PCI2_MEM_PHYS
- SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
#endif
- /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ /* LBC window - maps 256M */
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 78c5895..d33ef7e 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -53,10 +53,10 @@ int checkboard (void)
uint cpu_board_rev = get_cpu_board_revision ();
- printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
- get_board_version (), pci_slot);
-
- printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ puts("Board: MPC8548CDS");
+ printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
+ get_board_version(), pci_slot);
+ printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
/*
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index b2c1b31..04e55b1 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -41,63 +41,66 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
+ /* TLB 1 */
/*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
+ * Entry 0: 16M Non-cacheable, guarded
+ * 0xff00_0000 16M FLASH(cover boot page)
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
/*
- * TLB 1: 1G Non-cacheable, guarded
- * 0x80000000 1G PCI1/PCIE 8,9,a,b
+ * Entry 1: 1M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1G, 1),
+ 0, 1, BOOKE_PAGESZ_1M, 1),
/*
- * TLB 2: 256M Non-cacheable, guarded
+ * Entry 2: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
+ CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 2, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 3: 256M Non-cacheable, guarded
+ * Entry 3: 1M Non-cacheable, guarded
+ * 0xf800_0000 1M CADMUS registers
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
+ 0, 3, BOOKE_PAGESZ_1M, 1),
/*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 1M PCI1 IO
- * 0xe210_0000 1M PCI2 IO
- * 0xe300_0000 1M PCIe IO
+ * Entry 4: 1G Non-cacheable, guarded
+ * 0x8000_0000 256M PCI1 MEM
+ * 0x9000_0000 256M PCI2 MEM
+ * 0xa000_0000 512M PCIe MEM
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
+ 0, 4, BOOKE_PAGESZ_1G, 1),
/*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
+ * Entry 5: 16M Non-cacheable, guarded
+ * 0xe200_0000 8M PCI1 IO
+ * 0xe280_0000 8M PCI2 IO
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_64M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
/*
- * TLB 7: 64M Non-cacheable, guarded
- * 0xf8000000 64M CADMUS registers, relocated L2SRAM
+ * Entry 6: 16M Non-cacheable, guarded
+ * 0xe300_0000 16M PCIe IO
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_64M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 2760af0..235c7bb 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -141,16 +141,20 @@ extern unsigned long get_clock_freq(void);
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
-#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
+#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BR0_PRELIM 0xff801001
-#define CONFIG_SYS_BR1_PRELIM 0xff001001
+#define CONFIG_SYS_BR0_PRELIM \
+ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \
+ | BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR1_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR0_PRELIM 0xff806e65
#define CONFIG_SYS_OR1_PRELIM 0xff806e65
-#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+ {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
@@ -168,12 +172,8 @@ extern unsigned long get_clock_freq(void);
/*
* SDRAM on the Local Bus
*/
-#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
-#define CONFIG_SYS_LBC_CACHE_SIZE 64
-#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
-#define CONFIG_SYS_LBC_NONCACHE_SIZE 64
-
-#define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
@@ -194,7 +194,9 @@ extern unsigned long get_clock_freq(void);
* FIXME: the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861
+#define CONFIG_SYS_BR2_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
+ | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
@@ -265,15 +267,15 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_FSL_CADMUS
#define CADMUS_BASE_ADDR 0xf8000000
-#define CONFIG_SYS_BR3_PRELIM 0xf8000801
+#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
+#define CONFIG_SYS_BR3_PRELIM \
+ (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
-
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
@@ -326,27 +328,24 @@ extern unsigned long get_clock_freq(void);
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
-#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
-
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
#ifdef CONFIG_PCI2
-#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCI2_MEM_VIRT 0x90000000
+#define CONFIG_SYS_PCI2_MEM_BUS 0x90000000
+#define CONFIG_SYS_PCI2_MEM_PHYS 0x90000000
+#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000
#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI2_IO_SIZE 0x00800000 /* 8M */
#endif
#ifdef CONFIG_PCIE1
@@ -358,15 +357,14 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x01000000 /* 16M */
#endif
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_LEGACY
--
1.6.4.1
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