[U-Boot] [PATCH 08/12] blackfin: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy at chromium.org>
Cc: Mike Frysinger <vapier at gentoo.org>
Cc: Lukasz Majewski <l.majewski at samsung.com>

Change-Id: Ibdc2483c66c50d698108b790dd204fae38c7cb48
---
 arch/blackfin/include/asm/cache.h |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)
 create mode 100644 arch/blackfin/include/asm/cache.h

diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
new file mode 100644
index 0000000..f166c29
--- /dev/null
+++ b/arch/blackfin/include/asm/cache.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_CACHE_H__
+#define __BLACKFIN_CACHE_H__
+
+/*
+ * The blackfin architecture has a 32-byte L1 data cache line size.  Unless the
+ * board configuration has overridden this value we use it for aligning DMA
+ * buffers.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	32
+#endif
+
+#endif /* __BLACKFIN_CACHE_H__ */
-- 
1.7.3.1