[U-Boot] [PATCH 06/12] sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy at chromium.org>
Cc: Mike Frysinger <vapier at gentoo.org>
Cc: Lukasz Majewski <l.majewski at samsung.com>
Cc: Daniel Hellstrom <daniel at gaisler.com>

Change-Id: If33383ff88e0555204c4ed1534d3961587fdee3a
---
 arch/sparc/include/asm/cache.h |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h
index 03e8d94..44870e8 100644
--- a/arch/sparc/include/asm/cache.h
+++ b/arch/sparc/include/asm/cache.h
@@ -28,4 +28,14 @@
 #include <linux/config.h>
 #include <asm/processor.h>
 
+/*
+ * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
+ * use 32-bytes, the cacheline size for Sparc.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	32
+#endif
+
 #endif
-- 
1.7.3.1