[U-Boot] [PATCH 00/12] Define ARCH_DMA_MINALIGN for all architectures

[Kumar Gala]

On Oct 12, 2011, at 4:01 PM, Anton Staaf wrote:

> ARCH_DMA_MINALIGN is a new define borrowed from the Linux kernel.  It is
> used to define the minimum alignement requirement for a DMA buffer.  This
> series of patches ensures that it will always be defined in the arch specific
> asm/cache.h header and that asm/cache.h is included in common.h.  I chose to
> add this new define instead of reusing CONFIG_SYS_CACHELINE_SIZE for two
> reasons.  First, CONFIG_SYS_CACHELINE_SIZE is not defined for all architectures
> and thus to use it I would have to first define it correctly for all used
> architectures.  I wasn't quite up to that task right now.  Defining
> ARCH_DMA_MINALIGN is easier because it has slightly different semantics that
> allow it to be the maximum cacheline size known for an architecture.  And
> secondly, CONFIG_SYS_CACHELINE_SIZE may not always be the correct value to use
> to align DMA buffers.  In particular, on cache coherent architectures you can
> define ARCH_DMA_MINALIGN as 1 and be safe (unless there are other restrictions
> such as PCI alignment requirements).
> 
> This patch set will allow me to resubmit my ALLOC_CACHE_ALIGN_BUFFER patch set
> modified to use this new define in place of CONFIG_SYS_CACHELINE_SIZE.  I will
> repost those patches based on this set shortly.

I haven't looked at this patchset you reference, but what is causing the need for buffer alignment?

I question if on PPC we really need this to be at a cache line granularity.

- k