[U-Boot] [PATCH 1/3] powerpc/p5020: fixup portal config info

[Kumar Gala]

On Oct 12, 2011, at 4:39 PM, Kumar Gala wrote:

> From: Haiying Wang <Haiying.Wang at freescale.com>
> 
> P5020 has 10 qman portals, we need to configure all of them:
> * As there are only 2 physical cores sdest can only be 0 or 1
> * We assign dqrr & frame data LIODNs for all portals so if they
>  are utilized the proper mapping tables can be setup uniquely
>  (PAMU stashing)
> * We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
>  assignments are tuned around an assumption of at most 5
>  partitions.
> 
> Signed-off-by: Haiying Wang <Haiying.Wang at freescale.com>
> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/p5020_ids.c |   20 ++++++++++----------
> 1 files changed, 10 insertions(+), 10 deletions(-)

applied

- k