[U-Boot] [PATCH v2 01/11] arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Anton Staaf
robotboy at chromium.org
Tue Oct 18 01:46:03 CEST 2011
Signed-off-by: Anton Staaf <robotboy at chromium.org>
Cc: Mike Frysinger <vapier at gentoo.org>
Cc: Lukasz Majewski <l.majewski at samsung.com>
Cc: Albert ARIBAUD <albert.u.boot at aribaud.net>
---
arch/arm/include/asm/cache.h | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index d0518be..eef6a5a 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -42,4 +42,15 @@ static inline void invalidate_l2_cache(void)
void l2_cache_enable(void);
void l2_cache_disable(void);
+/*
+ * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
+ * use that value for aligning DMA buffers unless the board config has specified
+ * an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 64
+#endif
+
#endif /* _ASM_CACHE_H */
--
1.7.3.1
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