[U-Boot] [PATCH v2 03/11] nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Anton Staaf
robotboy at chromium.org
Tue Oct 18 01:46:05 CEST 2011
Signed-off-by: Anton Staaf <robotboy at chromium.org>
Cc: Mike Frysinger <vapier at gentoo.org>
Cc: Lukasz Majewski <l.majewski at samsung.com>
Cc: Scott McNutt <smcnutt at psyent.com>
---
arch/nios2/include/asm/cache.h | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/nios2/include/asm/cache.h b/arch/nios2/include/asm/cache.h
index c78f343..2cc16e4 100644
--- a/arch/nios2/include/asm/cache.h
+++ b/arch/nios2/include/asm/cache.h
@@ -27,4 +27,15 @@
extern void flush_dcache (unsigned long start, unsigned long size);
extern void flush_icache (unsigned long start, unsigned long size);
+/*
+ * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32
+ * bytes. If the board configuration has not specified one we default to the
+ * largest of these values for alignment of DMA buffers.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 32
+#endif
+
#endif /* __ASM_NIOS2_CACHE_H_ */
--
1.7.3.1
More information about the U-Boot
mailing list