[U-Boot] [PATCH v4 06/11] spl, nand: add 4bit HW ecc oob first nand_read_page function

[Heiko Schocher]

similiar to commit dc7cd8e59ba077f3b4c1a4557c9cd86a31b9ab1f, only
adapted for the new spl framework.

Signed-off-by: Heiko Schocher <hs at denx.de>
Acked-by: Tom Rini <trini at ti.com>
Cc: Scott Wood <scottwood at freescale.com>
Cc: Albert ARIBAUD <albert.u.boot at aribaud.net>
Cc: Sandeep Paulraj <s-paulraj at ti.com>

---
changes for v2:
- add comment from Scott Wood:
  as BSS is cleared, no need for intializing vars with 0
  remove this.

changes for v3:
- add comment from Scoot Wood and Tom Rini
  - rename CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST to
    CONFIG_SYS_NAND_HW_ECC_OOBFIRST
  - add dokumentation in README

changes for v4:
- added Acked-by: Tom Rini <trini at ti.com>

 README                             |    5 ++++
 drivers/mtd/nand/nand_spl_simple.c |   43 +++++++++++++++++++++++++++++++++++-
 2 files changed, 47 insertions(+), 1 deletions(-)

diff --git a/README b/README
index 65875c1..fa28a3c 100644
--- a/README
+++ b/README
@@ -3179,6 +3179,11 @@ Low Level (hardware related) configuration options:
 		that is executed before the actual U-Boot. E.g. when
 		compiling a NAND SPL.
 
+- CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+		define this, if you want to read first the oob data
+		and then the data. This is used for example on
+		davinci plattforms.
+
 - CONFIG_USE_ARCH_MEMCPY
   CONFIG_USE_ARCH_MEMSET
 		If these options are used a optimized version of memcpy/memset will
diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index 71491d4..e5003e6 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -140,6 +140,47 @@ static int nand_is_bad_block(int block)
 	return 0;
 }
 
+#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
+static int nand_read_page(int block, int page, uchar *dst)
+{
+	struct nand_chip *this = mtd.priv;
+	u_char *ecc_calc;
+	u_char *ecc_code;
+	u_char *oob_data;
+	int i;
+	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
+	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
+	uint8_t *p = dst;
+	int stat;
+
+	/*
+	 * No malloc available for now, just use some temporary locations
+	 * in SDRAM
+	 */
+	ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
+	ecc_code = ecc_calc + 0x100;
+	oob_data = ecc_calc + 0x200;
+
+	nand_command(block, page, 0, NAND_CMD_READOOB);
+	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+	nand_command(block, page, 0, NAND_CMD_READ0);
+
+	/* Pick the ECC bytes out of the oob data */
+	for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
+		ecc_code[i] = oob_data[nand_ecc_pos[i]];
+
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		this->ecc.hwctl(&mtd, NAND_ECC_READ);
+		this->read_buf(&mtd, p, eccsize);
+		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+		stat = this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+	}
+
+	return 0;
+}
+#else
 static int nand_read_page(int block, int page, void *dst)
 {
 	struct nand_chip *this = mtd.priv;
@@ -186,6 +227,7 @@ static int nand_read_page(int block, int page, void *dst)
 
 	return 0;
 }
+#endif
 
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 {
@@ -230,7 +272,6 @@ void nand_init(void)
 	mtd.priv = &nand_chip;
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
-	nand_chip.options = 0;
 	board_nand_init(&nand_chip);
 
 	if (nand_chip.select_chip)
-- 
1.7.6.4