[U-Boot] [PATCH 2/3] nds32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

[Macpaul Lin]

Add ARCH_DMA_MINALIGN definition to asm/cache.h

Signed-off-by: Macpaul Lin <macpaul at andestech.com>
---
 arch/nds32/include/asm/cache.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
index d769196..fc22c7b 100644
--- a/arch/nds32/include/asm/cache.h
+++ b/arch/nds32/include/asm/cache.h
@@ -51,4 +51,15 @@ DEFINE_GET_SYS_REG(DCM_CFG);
 #define DCM_CFG_OFF_DSZ	6	/* D-cache line size */
 #define DCM_CFG_MSK_DSZ	(0x7UL << DCM_CFG_OFF_DSZ)
 
+/*
+ * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	32
+#endif
+
 #endif /* _ASM_CACHE_H */
-- 
1.7.3.5