[U-Boot] [PATCH V2] ARM: orion5x: reduce dependence of including platform file
Lei Wen
leiwen at marvell.com
Wed Oct 26 04:22:20 CEST 2011
For files like the drivers/serial/serial.c, it must include the
platform file, as the CONFIG_SYS_NS16550_COM1 must reference to
the definition in the platform definition files.
Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.
Signed-off-by: Lei Wen <leiwen at marvell.com>
---
Changelog:
V2: seperate orion5x define structure as kirkwood and armada does
arch/arm/cpu/arm926ejs/orion5x/cpu.c | 2 +
arch/arm/cpu/arm926ejs/orion5x/dram.c | 1 +
arch/arm/cpu/arm926ejs/orion5x/timer.c | 1 +
arch/arm/include/asm/arch-orion5x/config.h | 135 ++++++++++++++++++++++
arch/arm/include/asm/arch-orion5x/orion5x.h | 6 -
common/cmd_ide.c | 6 -
include/configs/edminiv2.h | 166 +--------------------------
7 files changed, 141 insertions(+), 176 deletions(-)
create mode 100644 arch/arm/include/asm/arch-orion5x/config.h
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
index 05bd45c..2b0c760 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -28,7 +28,9 @@
#include <common.h>
#include <netdev.h>
#include <asm/cache.h>
+#include <asm/io.h>
#include <u-boot/md5.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/orion5x.h>
#include <hush.h>
diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c
index 5cc31a9..028f046 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/dram.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <config.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/orion5x.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c
index 17df68f..0b49b69 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c
@@ -25,6 +25,7 @@
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/arch/orion5x.h>
#define UBOOT_CNTR 0 /* counter to use for uboot timer */
diff --git a/arch/arm/include/asm/arch-orion5x/config.h b/arch/arm/include/asm/arch-orion5x/config.h
new file mode 100644
index 0000000..6db3554
--- /dev/null
+++ b/arch/arm/include/asm/arch-orion5x/config.h
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen at marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for Orion platform
+ */
+
+#ifndef _ORION_CONFIG_H
+#define _ORION_CONFIG_H
+
+#include <asm/arch/orion5x.h>
+#define MV_UART_CONSOLE_BASE ORION5X_UART0_BASE
+
+/*
+ * Board-specific values for Orion5x MPP low level init:
+ * - MPPs 12 to 15 are SATA LEDs (mode 5)
+ * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
+ * MPP16 to MPP19, mode 0 for others
+ */
+
+#define ORION5X_MPP0_7 0x00000003
+#define ORION5X_MPP8_15 0x55550000
+#define ORION5X_MPP16_23 0x00005555
+
+/*
+ * Board-specific values for Orion5x GPIO low level init:
+ * - GPIO3 is input (RTC interrupt)
+ * - GPIO16 is Power LED control (0 = on, 1 = off)
+ * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
+ * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
+ * - Last GPIO is 26, further bits are supposed to be 0.
+ * Enable mask has ones for INPUT, 0 for OUTPUT.
+ * Default is LED ON.
+ */
+
+#define ORION5X_GPIO_OUT_ENABLE 0x03fcffff
+#define ORION5X_GPIO_OUT_VALUE 0x03fcffff
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_NR_DRAM_BANKS_MAX 1
+/*
+ * FLASH configuration
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BASE 0xfff80000
+#define CONFIG_SYS_FLASH_SECTSZ \
+ {16384, 8192, 8192, 32768, \
+ 65536, 65536, 65536, 65536, 65536, 65536, 65536}
+
+/*
+ * Network
+ */
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE /* Enable Marvell GbE Driver */
+#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
+#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
+#define CONFIG_PHY_BASE_ADR 0x8
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#endif
+
+/*
+ * IDE
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+/* ED Mini V has an IDE-compatible SATA connector for port 1 */
+#define CONFIG_MVSATA_IDE
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE 4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* A single bus, a single device */
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
+/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
+#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
+/* end of IDE defines */
+#endif /* CMD_IDE */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+#endif /* _ORION_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h
index 9aeef88..18225b9 100644
--- a/arch/arm/include/asm/arch-orion5x/orion5x.h
+++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
@@ -30,13 +30,7 @@
#ifndef _ASM_ARCH_ORION5X_H
#define _ASM_ARCH_ORION5X_H
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/io.h>
-#endif /* __ASSEMBLY__ */
-
#if defined(CONFIG_FEROCEON)
-#include <asm/arch/cpu.h>
/* SOC specific definations */
#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index da5189c..d909c54 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -46,12 +46,6 @@
#include <mpc5xxx.h>
#endif
-#ifdef CONFIG_ORION5X
-#include <asm/arch/orion5x.h>
-#elif defined CONFIG_KIRKWOOD
-#include <asm/arch/kirkwood.h>
-#endif
-
#include <ide.h>
#include <ata.h>
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index f8affa8..255e4fd 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -46,150 +46,14 @@
#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
/*
- * CLKs configurations
- */
-
-#define CONFIG_SYS_HZ 1000
-
-/*
- * Board-specific values for Orion5x MPP low level init:
- * - MPPs 12 to 15 are SATA LEDs (mode 5)
- * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
- * MPP16 to MPP19, mode 0 for others
- */
-
-#define ORION5X_MPP0_7 0x00000003
-#define ORION5X_MPP8_15 0x55550000
-#define ORION5X_MPP16_23 0x00005555
-
-/*
- * Board-specific values for Orion5x GPIO low level init:
- * - GPIO3 is input (RTC interrupt)
- * - GPIO16 is Power LED control (0 = on, 1 = off)
- * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
- * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
- * - Last GPIO is 26, further bits are supposed to be 0.
- * Enable mask has ones for INPUT, 0 for OUTPUT.
- * Default is LED ON.
- */
-
-#define ORION5X_GPIO_OUT_ENABLE 0x03fcffff
-#define ORION5X_GPIO_OUT_VALUE 0x03fcffff
-
-/*
- * NS16550 Configuration
- */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
-
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
-
-/*
- * FLASH configuration
- */
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_BASE 0xfff80000
-#define CONFIG_SYS_FLASH_SECTSZ \
- {16384, 8192, 8192, 32768, \
- 65536, 65536, 65536, 65536, 65536, 65536, 65536}
-
-/* auto boot */
-#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-
-#define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
-/*
* Commands configuration - using default command set for now
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_IDE
#define CONFIG_CMD_I2C
-/*
- * Network
- */
-
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE /* Enable Marvell GbE Driver */
-#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
-#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
-#define CONFIG_PHY_BASE_ADR 0x8
-#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
-#endif
-
-/*
- * IDE
- */
-#ifdef CONFIG_CMD_IDE
-#define __io
-#define CONFIG_IDE_PREINIT
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-/* ED Mini V has an IDE-compatible SATA connector for port 1 */
-#define CONFIG_MVSATA_IDE
-#define CONFIG_MVSATA_IDE_USE_PORT1
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
-/* Data, registers and alternate blocks are at the same offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
-/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE 4
-/* Controller supports 48-bits LBA addressing */
-#define CONFIG_LBA48
-/* A single bus, a single device */
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
-/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
-#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
-/* end of IDE defines */
-#endif /* CMD_IDE */
-
-/*
- * I2C related stuff
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
-#endif
+#include "mv-common.h"
+#undef CONFIG_BOARD_EARLY_INIT_F
/*
* Environment variables configurations
@@ -199,30 +63,4 @@
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
-
-/*
- * Other required minimal configurations
- */
-#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
-#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_STACKSIZE 0x00100000
-#define CONFIG_SYS_LOAD_ADDR 0x00800000
-#define CONFIG_SYS_MEMTEST_START 0x00400000
-#define CONFIG_SYS_MEMTEST_END 0x007fffff
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
-#define CONFIG_SYS_MAXARGS 16
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
#endif /* _CONFIG_EDMINIV2_H */
--
1.7.0.4
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