[U-Boot] [PATCH 2/2] Powerpc/i2c: Force i2c to become bus master out of reset

[Huang Changming-R66093]

> > > >
> > > > The above sequence is different than the kernel version, why?
> > >
> > > I don't know the kernel version, but I write the u-boot code
> according
> > > to the Reference Manual of PowerPC, e.g p1022:
> > > 11.5.6 Generation of SCL When SDA Low
> > > It is sometimes necessary to force the I2C module to become the I2C
> bus
> > > master out of reset and drive SCL(even though SDA may already be
> driven,
> > > which indicates that the bus is busy). This can occur when a system
> > > reset does not cause all I2C devices to be reset. Thus, SDA can be
> > > driven low by another I2C device while this I2C module is coming
> out of
> > > reset and stays low indefinitely. The following procedure can be
> used
> > > to force this I2C module to generate SCL so that the device driving
> SDA
> > > can finish its transaction:
> > > 1. Disable the I2C module and set the master bit by setting I2CCR
> to
> > > 0x20
> > > 2. Enable the I2C module by setting I2CCR to 0xA0
> > > 3. Read the I2CDR
> > > 4. Return the I2C module to slave mode by setting I2CCR to 0x80
> > >
> > Compare with kernel version, the difference is one line:
> > Uboot:  readb(&dev->dr);
> > Kernel has no any operation.
> > But, I check the comment of kernel, because the 9th clock pulse isn't
> generated,
> > the sequence of function mpc_i2c_fixup is needed to generate 9th
> clock pulse.
> 
> Not so, there is more than that if you look closer. The description in
> the kernel
> is a bit misleading(or so I think). I prefer the kernel version for 2
> reasons:
> 1) It has been there for quite some time so if there were something
> wrong with,
>    it should have been noticed by now.
> 2) I have a vauge memory of checking it again the mpc8321 manual and I
> was happy
>    with it.
> 
These tow part codes are doing the different thing due to the different reason:
1. Kernel's code:
because Sometimes 9th clock pulse isn't generated, that code is to generate the 9th clock pulse.
It happens in the DATA transfer stage.
2. My code:
because the system reset does not cause all I2C devices to be reset, the code force the i2c to become the master and drive the SCL.
It happens in the i2c controller initialize stage
So, I think these code is reasonable.
 
BTW: My codes has been verified on Emerson's board.