[U-Boot] [PATCH 2/2] armada100: define CONFIG_SYS_CACHELINE_SIZE

[Lei Wen]

By default, on Armada100 SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 arch/arm/include/asm/arch-armada100/config.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
index d2094e5..637f313 100644
--- a/arch/arm/include/asm/arch-armada100/config.h
+++ b/arch/arm/include/asm/arch-armada100/config.h
@@ -33,6 +33,8 @@
 
 #include <asm/arch/armada100.h>
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
+/* default Dcache Line length for armada100 */
+#define CONFIG_SYS_CACHELINE_SIZE       32
 
 #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
 #define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
-- 
1.7.0.4