[U-Boot] PCIe on the i.MX6?

[Greg Topmiller]

Hi Carolyn,

I saw your message on the Denx mailing list.

I have the Novpek board with the MX6 quad on it and a full PCIe interface.  I am working in the Freescale Linux kernel and to get the interface to work we had to change a clock source for the PCIe.  We had to use the LVDS2 as SATA clock source rather than LVDS1 as SATA.  This is controlled by the PMU_MISC1 register at offset 0x20c8160.  In the reference manual it's section 49.7.6, page 4413.  Set the LVDS2_CLK_SEL (bits 9-5) field to SATA (010011b).  The original code set LVDS1_CLK_SEL (bits 4-0) to SATA(010011b).  Hope this helps.

Our current problem is getting a PCIe switch to work with the MX6.  The upstream port config space is available but the down stream is not.  0x1f00000 is exposed as the upstream config space but I expected the down stream to be at 0x1f10000 but nothing there.  Let me know if you have any ideas.  Have you tried a PCIe switch yet?

Thanks,

Greg Topmiller
Staff Software Engineer
240-404-2620
Greg.topmiller at jdsu.com


>Yes, I have the PCI clocks on. I can read the config space and can see the
>PCIe bus traffic using a logic analyzer when I do so. When I try reading
>memory or I/O space, I don't see any bus traffic.
>
>Thanks,
>Carolyn
>
>On Thu, Nov 1, 2012 at 11:18 AM, Fabio Estevam <festevam at gmail.com> wrote:
>
>> On Thu, Nov 1, 2012 at 2:32 PM, Carolyn Smith <carolynsmi56 at gmail.com>
>> wrote:
>> > Hello,
>> >
>> > Does anyone have any experience with PCIe on an i.MX6 processor (in
>> > particular the i.MX6 Solo)?
>> >
>> > I can access the config space of my PCIe device but can't seem to get its
>> > BARs mapped in properly. I thought I had the viewports set up but when I
>> > try to access the space, I just get a processor lockup.
>>
>> Have you turned on the PCI clocks?
>>