[U-Boot] [PATCH v2 08/13] ehci-mxc: Make EHCI power/oc polarities configurable
Benoît Thébaudeau
benoit.thebaudeau at advansee.com
Thu Nov 8 21:29:58 CET 2012
Make EHCI power and overcurrent polarities configurable. If not set, these new
configurartions keep the default register values so that existing board files
do not have to be changed.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau at advansee.com>
Cc: Marek Vasut <marex at denx.de>
Cc: Stefano Babic <sbabic at denx.de>
---
Changes for v2: None.
.../drivers/usb/host/ehci-mx5.c | 51 ++++++++++++++++++++
.../include/usb/ehci-fsl.h | 10 ++--
2 files changed, 57 insertions(+), 4 deletions(-)
diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
index 7da1398..52aeae5 100644
--- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c
@@ -44,24 +44,33 @@
/* USB_CTRL */
#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* OTG power pin polarity */
#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* HOST1 power pin polarity */
/* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */
#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */
#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */
/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
/* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
+#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
/* USB_CTRL_1 */
#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
@@ -151,12 +160,22 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
if (flags & MXC_EHCI_INTERNAL_PHY) {
v = __raw_readl(usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
+ else
+ v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
/* OC/USBPWR is used */
v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
else
/* OC/USBPWR is not used */
v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+#ifdef CONFIG_MX51
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
+ else
+ v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
@@ -167,6 +186,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
else
v |= MXC_OTG_UCTRL_OPM_BIT;
#endif
+#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
+ else
+ v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
@@ -186,9 +211,19 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
else
v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
#endif
+#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
+ else
+ v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H1_OC_POL_BIT;
+ else
+ v &= ~MXC_H1_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
else
@@ -205,10 +240,18 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
#endif
#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
+ else
+ v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
else
v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
+ else
+ v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
#endif
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
@@ -216,10 +259,18 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
#ifdef CONFIG_MX53
case 3: /* Host 3 ULPI */
v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
+ else
+ v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
else
v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
+ else
+ v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
break;
diff --git u-boot-usb-76454b2.orig/include/usb/ehci-fsl.h u-boot-usb-76454b2/include/usb/ehci-fsl.h
index 4dee5b0..a1438d6 100644
--- u-boot-usb-76454b2.orig/include/usb/ehci-fsl.h
+++ u-boot-usb-76454b2/include/usb/ehci-fsl.h
@@ -266,11 +266,13 @@ struct usb_ehci {
#define MXC_EHCI_INTERFACE_MASK (0xf)
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
-#define MXC_EHCI_TTL_ENABLED (1 << 6)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
+#define MXC_EHCI_TTL_ENABLED (1 << 8)
-#define MXC_EHCI_INTERNAL_PHY (1 << 7)
-#define MXC_EHCI_IPPUE_DOWN (1 << 8)
-#define MXC_EHCI_IPPUE_UP (1 << 9)
+#define MXC_EHCI_INTERNAL_PHY (1 << 9)
+#define MXC_EHCI_IPPUE_DOWN (1 << 10)
+#define MXC_EHCI_IPPUE_UP (1 << 11)
/* Board-specific initialization */
int board_ehci_hcd_init(int port);
More information about the U-Boot
mailing list