[U-Boot] [PATCH] mx28: Remove SET, CLR, TOG ops from PLLxCTRL1 registers

[Marek Vasut]

These registers don't have _SET, _CLR and _TOG at the respective offsets
available, these registers has to be toggled via R-M-W if needed. Thus do
not export these offsets anymore.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Stefano Babic <sbabic at denx.de>
---
 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
index b662fbe..23e9adc 100644
--- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
@@ -31,9 +31,11 @@
 #ifndef	__ASSEMBLY__
 struct mxs_clkctrl_regs {
 	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
-	mxs_reg_32(hw_clkctrl_pll0ctrl1)	/* 0x10 */
+	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
+	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
 	mxs_reg_32(hw_clkctrl_pll1ctrl0)	/* 0x20 */
-	mxs_reg_32(hw_clkctrl_pll1ctrl1)	/* 0x30 */
+	uint32_t	hw_clkctrl_pll1ctrl1;	/* 0x30 */
+	uint32_t	reserved_pll1ctrl1[3];	/* 0x34-0x3c */
 	mxs_reg_32(hw_clkctrl_pll2ctrl0)	/* 0x40 */
 	mxs_reg_32(hw_clkctrl_cpu)		/* 0x50 */
 	mxs_reg_32(hw_clkctrl_hbus)		/* 0x60 */
-- 
1.7.10.4