[U-Boot] [PATCH v2] am335x:Handle worst case scenario for Errata 1.0.24
Tom Rini
trini at ti.com
Wed Aug 14 16:51:31 CEST 2013
From: Steve Kipisz <s-kipisz2 at ti.com>
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
the boot ROM sets the frequencies for OPP100. This patch attempts to
drop the frequencies back to OPP50 as soon as possible in the SPL. Then
later the voltages and frequencies up set higher.
Cc: Enric Balletbo i Serra <eballetbo at iseebcn.com>
Cc: Lars Poeschel <poeschel at lemonage.de>
Signed-off-by: Steve Kipisz <s-kipisz2 at ti.com>
[trini: Adapt to current framework]
Signed-off-by: Tom Rini <trini at ti.com>
---
Changes in v2:
- Address Dan Murphy's comments
---
arch/arm/cpu/armv7/am33xx/board.c | 2 +
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 72 ++++++++++++++--------
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 3 +
arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 +
board/ti/am335x/board.c | 12 ++++
include/configs/pcm051.h | 1 +
include/power/tps65217.h | 1 +
7 files changed, 68 insertions(+), 24 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 88e2093..e94b038 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -150,6 +150,8 @@ int arch_misc_init(void)
*/
__weak void am33xx_spl_board_init(void)
{
+ mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+ core_pll_config(OPP_100);
}
void rtc32k_enable(void)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index fb3fb43..f623004 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -42,12 +42,17 @@
/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000
+#define COREPLL_M_OPP50 50
#define COREPLL_N (OSC-1)
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
+#define COREPLL_M4_OPP50 1
+#define COREPLL_M5_OPP50 1
+#define COREPLL_M6_OPP50 1
+
/*
* USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
* frequency needs to be set to 960 MHZ. Hence,
@@ -266,12 +271,7 @@ void mpu_pll_config_val(int mpull_m)
;
}
-static void mpu_pll_config(void)
-{
- mpu_pll_config_val(CONFIG_SYS_MPUCLK);
-}
-
-static void core_pll_config(void)
+void core_pll_config(int opp)
{
u32 clkmode, clksel, div_m4, div_m5, div_m6;
@@ -285,29 +285,53 @@ static void core_pll_config(void)
writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
- ;
+ ;
+ if (opp == OPP_50) {
+ clksel = clksel & (~CLK_SEL_MASK);
+ clksel = clksel | ((COREPLL_M_OPP50 << CLK_SEL_SHIFT)
+ | COREPLL_N);
+ writel(clksel, &cmwkup->clkseldpllcore);
- clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
- writel(clksel, &cmwkup->clkseldpllcore);
+ div_m4 = div_m4 & ~CLK_DIV_MASK;
+ div_m4 = div_m4 | COREPLL_M4_OPP50;
+ writel(div_m4, &cmwkup->divm4dpllcore);
- div_m4 = div_m4 & ~CLK_DIV_MASK;
- div_m4 = div_m4 | COREPLL_M4;
- writel(div_m4, &cmwkup->divm4dpllcore);
+ div_m5 = div_m5 & ~CLK_DIV_MASK;
+ div_m5 = div_m5 | COREPLL_M5_OPP50;
+ writel(div_m5, &cmwkup->divm5dpllcore);
- div_m5 = div_m5 & ~CLK_DIV_MASK;
- div_m5 = div_m5 | COREPLL_M5;
- writel(div_m5, &cmwkup->divm5dpllcore);
+ div_m6 = div_m6 & ~CLK_DIV_MASK;
+ div_m6 = div_m6 | COREPLL_M6_OPP50;
+ writel(div_m6, &cmwkup->divm6dpllcore);
- div_m6 = div_m6 & ~CLK_DIV_MASK;
- div_m6 = div_m6 | COREPLL_M6;
- writel(div_m6, &cmwkup->divm6dpllcore);
+ clkmode = clkmode | CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllcore);
- clkmode = clkmode | CLK_MODE_SEL;
- writel(clkmode, &cmwkup->clkmoddpllcore);
+ while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
+ ;
+ } else {
+ clksel = clksel & (~CLK_SEL_MASK);
+ clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
+ writel(clksel, &cmwkup->clkseldpllcore);
+
+ div_m4 = div_m4 & ~CLK_DIV_MASK;
+ div_m4 = div_m4 | COREPLL_M4;
+ writel(div_m4, &cmwkup->divm4dpllcore);
+
+ div_m5 = div_m5 & ~CLK_DIV_MASK;
+ div_m5 = div_m5 | COREPLL_M5;
+ writel(div_m5, &cmwkup->divm5dpllcore);
+
+ div_m6 = div_m6 & ~CLK_DIV_MASK;
+ div_m6 = div_m6 | COREPLL_M6;
+ writel(div_m6, &cmwkup->divm6dpllcore);
+
+ clkmode = clkmode | CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllcore);
- while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
+ while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
;
+ }
}
static void per_pll_config(void)
@@ -390,8 +414,8 @@ void enable_emif_clocks(void)
*/
void pll_init()
{
- mpu_pll_config();
- core_pll_config();
+ mpu_pll_config_val(MPUPLL_M_300);
+ core_pll_config(OPP_50);
per_pll_config();
/* Enable the required interconnect clocks */
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 789188b..9a480d9 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -11,6 +11,9 @@
#ifndef _CLOCKS_AM33XX_H_
#define _CLOCKS_AM33XX_H_
+#define OPP_50 50
+#define OPP_100 100
+
/* MAIN PLL Fdll = 550 MHz, by default */
#ifndef CONFIG_SYS_MPUCLK
#define CONFIG_SYS_MPUCLK 550
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 1340f83..9c7647b 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -27,6 +27,7 @@ void save_omap_boot_params(void);
void setup_clocks_for_console(void);
void mpu_pll_config_val(int mpull_m);
void ddr_pll_config(unsigned int ddrpll_M);
+void core_pll_config(int opp);
void sdelay(unsigned long);
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index e7f14db..b0fa4b2 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -337,6 +337,15 @@ void am33xx_spl_board_init(void)
TPS65217_USB_INPUT_CUR_LIMIT_MASK))
puts("tps65217_reg_write failure\n");
+ /* Set DCDC3 (CORE) voltage to 1.125V */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /* Set CORE Frequencies to OPP100 */
+ core_pll_config(OPP_100);
/* Set DCDC2 (MPU) voltage */
if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
@@ -395,6 +404,9 @@ void am33xx_spl_board_init(void)
/* Second, update the CORE voltage. */
if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
return;
+
+ /* Set CORE Frequencies to OPP100 */
+ core_pll_config(OPP_100);
}
/* Set MPU Frequency to what we detected now that voltages are set */
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 9b16c47..f4b4d62 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -204,6 +204,7 @@
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
/*
* Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the
diff --git a/include/power/tps65217.h b/include/power/tps65217.h
index f4c7a2b..f3e067d 100644
--- a/include/power/tps65217.h
+++ b/include/power/tps65217.h
@@ -62,6 +62,7 @@
#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02
#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03
+#define TPS65217_DCDC_VOLT_SEL_1125MV 0x09
#define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F
#define TPS65217_DCDC_VOLT_SEL_1325MV 0x11
--
1.7.9.5
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