[U-Boot] Enabling L2 cache on mx53

[Dirk Behme]

Am 19.08.2013 15:55, schrieb Fabio Estevam:
> Hi,
>
> I notice slow tftp transfer on mx53qsb and I suspected it could be due
> to L2 cache being disabled.
>
> Tried enabling with:
>
> --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> @@ -45,6 +45,11 @@
>   #endif
>
>          mcr 15, 1, r0, c9, c0, 2
> +
> +       /* enable L2 cache */
> +       mrc 15, 0, r0, c1, c0, 1
> +       orr r0, r0, #(1 << 1)    /* enable l2 cache */
> +       mcr 15, 0, r0, c1, c0, 1
>   .endm /* init_l2cc */
>
>   /* AIPS setup - Only setup MPROTx registers.
>
>
> ,but still see the same low tftp throughput (720 kB/s - on mx28 I see
> the double rate).
>
> Any suggestions as to how properly enable L2 cache on mx53?

Is the mx53 L2 cache the same like on mx6?

If so, besides enabling it, it needs a proper configuration. Have a 
look to

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=5a5ca56e057d206db13461b84a7da3a3543e1206

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=b3a9c315378ff811bf34393f2f0a6e8b9ffced3b

Best regards

Dirk