[U-Boot] [RFC 1/3] ARM,crt0.S: call s_init instead from ctr0.S

[Jeroen Hofstee]

The only reason gd is setup before _main seems to be
the call to s_init. Therefore call s_init in crt0.S
after gd has been setup. (It might become system_init
one day, but that has the disadvantage that all versions
of board_init_f must call system_init).
---
 arch/arm/cpu/armv7/lowlevel_init.S         | 23 +----------------------
 arch/arm/cpu/armv7/omap3/lowlevel_init.S   |  8 ++++----
 arch/arm/cpu/armv7/rmobile/lowlevel_init.S |  6 ------
 arch/arm/lib/crt0.S                        |  3 +++
 arch/arm/lib/reset.c                       |  5 +++++
 board/ti/omap5912osk/lowlevel_init.S       | 11 -----------
 6 files changed, 13 insertions(+), 43 deletions(-)

diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index 82b2b86..1ec7481 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -16,26 +16,5 @@
 #include <linux/linkage.h>
 
 ENTRY(lowlevel_init)
-	/*
-	 * Setup a temporary stack
-	 */
-	ldr	sp, =CONFIG_SYS_INIT_SP_ADDR
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-#ifdef CONFIG_SPL_BUILD
-	ldr	r8, =gdata
-#else
-	sub	sp, #GD_SIZE
-	bic	sp, sp, #7
-	mov	r8, sp
-#endif
-	/*
-	 * Save the old lr(passed in ip) and the current lr to stack
-	 */
-	push	{ip, lr}
-
-	/*
-	 * go setup pll, mux, memory
-	 */
-	bl	s_init
-	pop	{ip, pc}
+	mov	pc, lr
 ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index bdf74ea..db1d4dc 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -197,22 +197,22 @@ pll_div_val5:
 #endif
 
 ENTRY(lowlevel_init)
+#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
 	ldr	sp, SRAM_STACK
 	str	ip, [sp]	/* stash ip register */
 	mov	ip, lr		/* save link reg across call */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
 /*
  * No need to copy/exec the clock code - DPLL adjust already done
  * in NAND/oneNAND Boot.
  */
 	ldr	r1, =SRAM_CLK_CODE
 	bl	cpy_clk_code
-#endif /* NAND Boot */
+
 	mov	lr, ip		/* restore link reg */
 	ldr	ip, [sp]	/* restore save ip */
-	/* tail-call s_init to setup pll, mux, memory */
-	b	s_init
+#endif /* NAND Boot */
 
+	mov	pc, lr
 ENDPROC(lowlevel_init)
 
 	/* the literal pools origin */
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
index ff18d96..70ec22d 100644
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
@@ -59,14 +59,8 @@ loop0:
 	subs r0, r0, #1
 	bne  loop0
 
-	ldr sp, MERAM_STACK
-	b s_init
-
 	.pool
 	.align 4
 
 ENDPROC(lowlevel_init)
 	.ltorg
-
-MERAM_STACK:
-	.word LOW_LEVEL_MERAM_STACK
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 960d12e..98d7881 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -70,6 +70,9 @@ ENTRY(_main)
 	sub	sp, #GD_SIZE	/* allocate one GD above SP */
 	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
 	mov	r8, sp		/* GD is above SP */
+
+	bl	s_init
+
 	mov	r0, #0
 	bl	board_init_f
 
diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
index 7a03580..d14eac9 100644
--- a/arch/arm/lib/reset.c
+++ b/arch/arm/lib/reset.c
@@ -35,3 +35,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	/*NOTREACHED*/
 	return 0;
 }
+
+/* HACK */
+__weak void s_init(void)
+{
+}
diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S
index cad0a5a..61c8605 100644
--- a/board/ti/omap5912osk/lowlevel_init.S
+++ b/board/ti/omap5912osk/lowlevel_init.S
@@ -296,17 +296,6 @@ common_tc:
 	ldr	sp,	SRAM_STACK
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
 
-	/*
-	 * Save the old lr(passed in ip) and the current lr to stack
-	 */
-	push	{ip, lr}
-
-	/*
-	 * go setup pll, mux, memory
-	 */
-	bl	s_init
-	pop	{ip, pc}
-
 	/* back to arch calling code */
 	mov	pc,	lr
 
-- 
1.8.1.2