[U-Boot] [PATCH v4 1/6] arm, am33xx: add defines for gmii_sel_register bits
Enric Balletbo Serra
eballetbo at gmail.com
Wed Aug 28 11:00:32 CEST 2013
Hi all,
Sorry for late reply, I was out of office.
2013/8/19 Tom Rini <trini at ti.com>:
> On Mon, Aug 19, 2013 at 04:38:56PM +0200, Heiko Schocher wrote:
>
>> Signed-off-by: Heiko Schocher <hs at denx.de>
>> Acked-by: Mugunthan V N <mugunthanvnm at ti.com>
>
> Looks fine, but can we get this tested on the isee board too? It's a
> functional change there (since it was setting the NOTUSED bit that HW
> folks say really should not be set and will be marked as reserved in the
> next TRM respin). Thanks!
>
With this patch the IGEP COM AQUILA works as expected. Thanks.
Tested-by: Enric Balletbo i Serra <eballetbo at iseebcn.com>
>>
>> ---
>> - changes for v2:
>> defined all bits used in the gmii_sel register as
>> Tom Rini suggested
>> - changes for v3:
>> rebased against u-boot-ti commit bb2a5d8f87fffb4fadfb205837decbd1b3e75f88
>> - changes for v4:
>> - rebased against u-boot-ti commit 425faf74cd8189c87919f7e72a0101c684ee3b9f
>> - add changes requested from Tom Rini:
>> - use <space> after "#define" instead <tab>
>> - rename struct name "reserved" to "resv1"
>> - remove GMII1_SEL_NOTUSED and GMII2_SEL_NOTUSED defines, also
>> the GMII2_SEL_NOTUSED usage on the igep0033 board
>> - add "Acked-by: Mugunthan V N <mugunthanvnm at ti.com>"
>> ---
>> arch/arm/include/asm/arch-am33xx/cpu.h | 19 +++++++++++++++++++
>> board/isee/igep0033/board.c | 6 ++----
>> board/phytec/pcm051/board.c | 2 --
>> board/ti/am335x/board.c | 6 +-----
>> 4 Dateien ge??ndert, 22 Zeilen hinzugef??gt(+), 11 Zeilen entfernt(-)
>>
>> diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
>> index 10b56e0..f77ac1e 100644
>> --- a/arch/arm/include/asm/arch-am33xx/cpu.h
>> +++ b/arch/arm/include/asm/arch-am33xx/cpu.h
>> @@ -486,6 +486,25 @@ struct ctrl_dev {
>> unsigned int resv4[4];
>> unsigned int miisel; /* offset 0x50 */
>> };
>> +
>> +/* gmii_sel register defines */
>> +#define GMII1_SEL_MII 0x0
>> +#define GMII1_SEL_RMII 0x1
>> +#define GMII1_SEL_RGMII 0x2
>> +#define GMII2_SEL_MII 0x0
>> +#define GMII2_SEL_RMII 0x4
>> +#define GMII2_SEL_RGMII 0x8
>> +#define RGMII1_IDMODE BIT(4)
>> +#define RGMII2_IDMODE BIT(5)
>> +#define RMII1_IO_CLK_EN BIT(6)
>> +#define RMII2_IO_CLK_EN BIT(7)
>> +
>> +#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
>> +#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
>> +#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
>> +#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
>> +#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
>> +
>> #endif /* __ASSEMBLY__ */
>> #endif /* __KERNEL_STRICT_NAMES */
>>
>> diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
>> index a24c22b..9e91f68 100644
>> --- a/board/isee/igep0033/board.c
>> +++ b/board/isee/igep0033/board.c
>> @@ -27,9 +27,6 @@
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> -/* MII mode defines */
>> -#define RMII_MODE_ENABLE 0x4D
>> -
>> static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
>>
>> #ifdef CONFIG_SPL_BUILD
>> @@ -158,7 +155,8 @@ int board_eth_init(bd_t *bis)
>> eth_setenv_enetaddr("ethaddr", mac_addr);
>> }
>>
>> - writel(RMII_MODE_ENABLE, &cdev->miisel);
>> + writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
>> + &cdev->miisel);
>>
>> rv = cpsw_register(&cpsw_data);
>> if (rv < 0)
>> diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
>> index f53c5bb..e40b0bd 100644
>> --- a/board/phytec/pcm051/board.c
>> +++ b/board/phytec/pcm051/board.c
>> @@ -31,8 +31,6 @@
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> /* MII mode defines */
>> -#define MII_MODE_ENABLE 0x0
>> -#define RGMII_MODE_ENABLE 0xA
>> #define RMII_RGMII2_MODE_ENABLE 0x49
>>
>> static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
>> diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
>> index 04c37e2..cc04426 100644
>> --- a/board/ti/am335x/board.c
>> +++ b/board/ti/am335x/board.c
>> @@ -30,10 +30,6 @@
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> -/* MII mode defines */
>> -#define MII_MODE_ENABLE 0x0
>> -#define RGMII_MODE_ENABLE 0x3A
>> -
>> /* GPIO that controls power to DDR on EVM-SK */
>> #define GPIO_DDR_VTT_EN 7
>>
>> @@ -460,7 +456,7 @@ int board_eth_init(bd_t *bis)
>> cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
>> PHY_INTERFACE_MODE_MII;
>> } else {
>> - writel(RGMII_MODE_ENABLE, &cdev->miisel);
>> + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
>> cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
>> PHY_INTERFACE_MODE_RGMII;
>> }
>> --
>> 1.7.11.7
>>
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>
> --
> Tom
>
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