[U-Boot] [PATCH 1/6] imx: mx6q DDR3 init: Fix tMRD

[Eric Nelson]

On 01/30/2013 02:19 PM, Benoît Thébaudeau wrote:
> MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
>
> For all DDR3 speed bins:
>    tMRD(min) = 4 nCK
>    tMOD(min) = max(12 nCK, 15 ns)
>
> Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK
> at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
>
> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau at advansee.com>
> ---
>   board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> index c86cd40..9ac8027 100644
> --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> @@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740
>
>   DATA 4 0x021b001c 0x00008000
>   DATA 4 0x021b000c 0x555A7975
> -DATA 4 0x021b0010 0xFF538E64
> +DATA 4 0x021b0010 0xFF538F64
>   DATA 4 0x021b0014 0x01FF00DB
>   DATA 4 0x021b002c 0x000026D2
>
>

Hi Benoît,

I've been able to confirm operation of this complete patch set
on a SABRE Lite here, but only that (boots normally).

I'll try to scare up a board we can place on an extended burn-in.

What prompted you to walk the list? Was there a specific failure
that this addressed?

Please advise,


Eric