[U-Boot] [PATCH V2 7/7] ARM: OMAP5: Clean up iosettings code
R Sricharan
r.sricharan at ti.com
Mon Feb 4 15:22:05 CET 2013
From: Lokesh Vutla <lokeshvutla at ti.com>
There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.
This avoids unnessecary code addition for future socs.
Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
---
arch/arm/cpu/armv7/omap5/hw_data.c | 36 +++++++++++++
arch/arm/cpu/armv7/omap5/hwinit.c | 75 +++++++++++----------------
arch/arm/include/asm/arch-omap5/omap.h | 10 ++++
arch/arm/include/asm/arch-omap5/sys_proto.h | 1 +
4 files changed, 78 insertions(+), 44 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 59c2283..6b039f5 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -32,6 +32,7 @@
#include <asm/arch/clocks.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
+#include <asm/emif.h>
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
@@ -414,6 +415,24 @@ void enable_non_essential_clocks(void)
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}
+const struct ctrl_ioregs ioregs_omap5430 = {
+ .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+ .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+ .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+};
+
+const struct ctrl_ioregs ioregs_omap5432_es1 = {
+ .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_lpddr2ch = 0x0,
+ .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+ .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+};
+
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
@@ -438,3 +457,20 @@ void hw_data_init(void)
*ctrl = &omap5_ctrl;
}
+
+void get_ioregs(const struct ctrl_ioregs **regs)
+{
+ u32 omap_rev = omap_revision();
+
+ switch (omap_rev) {
+ case OMAP5430_ES1_0:
+ *regs = &ioregs_omap5430;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = &ioregs_omap5432_es1;
+ break;
+
+ default:
+ printf("\n INVALID OMAP REVISION ");
+ }
+}
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 1863c69..dfc0e44 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -56,60 +56,47 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- (*ctrl)->control_ddrch1_0);
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- (*ctrl)->control_ddrch1_1);
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- (*ctrl)->control_ddrch2_0);
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- (*ctrl)->control_ddrch2_1);
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- (*ctrl)->control_lpddr2ch1_0);
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- (*ctrl)->control_lpddr2ch1_1);
- writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
- (*ctrl)->control_ddrio_0);
- writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
- (*ctrl)->control_ddrio_1);
- writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
- (*ctrl)->control_ddrio_2);
+ const struct ctrl_ioregs *ioregs;
+
+ get_ioregs(&ioregs);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
+ writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
+ writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
+ writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
}
/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
u32 io_settings = 0;
+ const struct ctrl_ioregs *ioregs;
- writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
- (*ctrl)->control_ddr3ch1_0);
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- (*ctrl)->control_ddrch1_0);
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- (*ctrl)->control_ddrch1_1);
-
- writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
- (*ctrl)->control_ddr3ch2_0);
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- (*ctrl)->control_ddrch2_0);
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- (*ctrl)->control_ddrch2_1);
-
- writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
- (*ctrl)->control_ddrio_0);
- writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
- (*ctrl)->control_ddrio_1);
- writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
- (*ctrl)->control_ddrio_2);
+ get_ioregs(&ioregs);
+ writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
+
+ writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
+
+ writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
+ writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
+ writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
/* omap5432 does not use lpddr2 */
- writel(0x0, (*ctrl)->control_lpddr2ch1_0);
- writel(0x0, (*ctrl)->control_lpddr2ch1_1);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
- writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
- (*ctrl)->control_emif1_sdram_config_ext);
- writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
- (*ctrl)->control_emif2_sdram_config_ext);
+ writel(ioregs->ctrl_emif_sdram_config_ext,
+ (*ctrl)->control_emif1_sdram_config_ext);
+ writel(ioregs->ctrl_emif_sdram_config_ext,
+ (*ctrl)->control_emif2_sdram_config_ext);
/* Disable DLL select */
io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index a91da7d..873ccd7 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -229,5 +229,15 @@ struct omap_boot_parameters {
unsigned char reset_reason;
unsigned char ch_flags;
};
+
+struct ctrl_ioregs {
+ u32 ctrl_ddrch;
+ u32 ctrl_lpddr2ch;
+ u32 ctrl_ddr3ch;
+ u32 ctrl_ddrio_0;
+ u32 ctrl_ddrio_1;
+ u32 ctrl_ddrio_2;
+ u32 ctrl_emif_sdram_config_ext;
+};
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 2b3a071..201ed6f 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -58,6 +58,7 @@ void omap_vc_init(u16 speed_khz);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
+void get_ioregs(const struct ctrl_ioregs **regs);
/*
* This is used to verify if the configuration header
--
1.7.9.5
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