[U-Boot] [PATCH v2 1/3] Tegra: I2C: Add T114 clock support to tegra_i2c driver

[Tom Warren]

T114 has a slightly different I2C clock, with a new divisor for
standard/fast mode and HS mode. Tested on my Dalmore, and the I2C
clock is 100KHz +/- 3% on my Saleae Logic analyzer.

Signed-off-by: Tom Warren <twarren at nvidia.com>
---
v2: new

 arch/arm/include/asm/arch-tegra/tegra_i2c.h |    6 ++++++
 drivers/i2c/tegra_i2c.c                     |   22 +++++++++++++++++++++-
 2 files changed, 27 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h
index 2650744..853e59b 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h
@@ -105,6 +105,7 @@ struct i2c_ctlr {
 	u32 sl_delay_count;		/* 3C: I2C_I2C_SL_DELAY_COUNT */
 	u32 reserved_2[4];		/* 40: */
 	struct i2c_control control;	/* 50 ~ 68 */
+	u32 clk_div;			/* 6C: I2C_I2C_CLOCK_DIVISOR */
 };
 
 /* bit fields definitions for IO Packet Header 1 format */
@@ -154,6 +155,11 @@ struct i2c_ctlr {
 #define I2C_INT_ARBITRATION_LOST_SHIFT	2
 #define I2C_INT_ARBITRATION_LOST_MASK	(1 << I2C_INT_ARBITRATION_LOST_SHIFT)
 
+/* I2C_CLK_DIVISOR_REGISTER */
+#define CLK_DIV_STD_FAST_MODE		0x19
+#define CLK_DIV_HS_MODE			1
+#define CLK_MULT_STD_FAST_MODE		8
+
 /**
  * Returns the bus number of the DVC controller
  *
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index efc77fa..0558648 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -88,7 +88,27 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
 	 * 16 to get the right frequency.
 	 */
 	clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
-			       i2c_bus->speed * 2 * 8);
+		i2c_bus->speed * 2 * 8);
+#if defined(CONFIG_TEGRA114)
+	/*
+	 * T114 I2C went to a single clock source for standard/fast and
+	 * HS clock speeds. The new clock rate setting calculation is:
+	 *  SCL = CLK_SOURCE.I2C /
+	 *   (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
+	 *   I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
+	 *
+	 * NOTE: We do this here, after the initial clock/pll start,
+	 * because if we read the clk_div reg before the controller
+	 * is running, we hang, and we need it for the new calc.
+	 */
+	int clk_div_std_fast_mode = readl(&i2c_bus->regs->clk_div) >> 16;
+	debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
+		clk_div_std_fast_mode);
+
+	clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
+		CLK_MULT_STD_FAST_MODE * (clk_div_std_fast_mode+1) *
+		i2c_bus->speed * 2);
+#endif	/* T114 */
 
 	/* Reset I2C controller. */
 	i2c_reset_controller(i2c_bus);
-- 
1.7.0.4